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2009 52nd IEEE International Midwest Symposium on Circuits and Systems最新文献

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An on-chip ramp generator for single-slope look ahead ramp (SSLAR) ADC 片上斜坡发生器用于单斜坡前视斜坡(SSLAR) ADC
2009 52nd IEEE International Midwest Symposium on Circuits and Systems Pub Date : 2009-09-15 DOI: 10.1109/MWSCAS.2009.5236076
S. Balagopal, S. Ay
{"title":"An on-chip ramp generator for single-slope look ahead ramp (SSLAR) ADC","authors":"S. Balagopal, S. Ay","doi":"10.1109/MWSCAS.2009.5236076","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5236076","url":null,"abstract":"An on-chip ramp generator was developed for single-slope look-ahead ramp (SSLAR) analog-to-digital converter (ADC) integrated in a column-parallel CMOS image sensor. Ramp generator is the central part of a new ADC algorithm which uses modified single-slope ramp (SSR) ADC timing. Ramp block designed such a way that it allows wide output voltage ranges as well as code hopping, code fall back and look-ahead operations in column-parallel ramp ADC. Ramp generator was fabricated using 0.5µm, 2P3M CMOS technology. Ramp generator composes of 10-bit synchronous counter, switched-capacitor based voltage steering circuits, output buffer and logic circuits. Effective layout area of ramp generator is 0.3mm2.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"173 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114662652","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A comparative analysis of coarse-grain and fine-grain power gating for FPGA lookup tables FPGA查找表的粗粒度和细粒度功率门控的比较分析
2009 52nd IEEE International Midwest Symposium on Circuits and Systems Pub Date : 2009-09-15 DOI: 10.1109/MWSCAS.2009.5236045
P. Nair, S. Koppa, E. John
{"title":"A comparative analysis of coarse-grain and fine-grain power gating for FPGA lookup tables","authors":"P. Nair, S. Koppa, E. John","doi":"10.1109/MWSCAS.2009.5236045","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5236045","url":null,"abstract":"Leakage power dissipation is becoming a concern in field-programmable gate arrays (FPGAs) due to scaling in FPGA technology. Widely available commercial FPGAs are based on lookup tables (LUTs) consisting of SRAM arrays and multiplexers. In this paper, we analyze the leakage power dissipation in the SRAM-array of a FPGA LUT for a 65nm CMOS process. We apply power-gating to an FPGA LUT SRAM array in two different ways, namely, coarse-grain power gating and fine-grain power gating. We carry out a comparative analysis of the two methods. In our research, we found that power-gating can be employed to drastically reduce the leakage power dissipation in the SRAM. More leakage savings were obtained with coarse-grain power-gating than with fine-grain power gating. The coarse-grain and fine-grain power-gating techniques yielded approximately 99 percent and 81 percent leakage savings, respectively, over the case where no power-gating is applied.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122114018","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Communication infrastructures to facilitate regional voltage control of active radial distribution networks 便于有源径向配电网区域电压控制的通信基础设施
2009 52nd IEEE International Midwest Symposium on Circuits and Systems Pub Date : 2009-09-15 DOI: 10.1109/MWSCAS.2009.5236096
Qiang Yang, J. Barria, Carlos A. Hernandez Aramburo
{"title":"Communication infrastructures to facilitate regional voltage control of active radial distribution networks","authors":"Qiang Yang, J. Barria, Carlos A. Hernandez Aramburo","doi":"10.1109/MWSCAS.2009.5236096","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5236096","url":null,"abstract":"The increasing penetration of distributed generators into passive medium voltage (MV) power distribution networks could bring enormous challenges in network management. An ongoing UK EPSRC research project, AuRA-NMS (autonomous regional active network management system), aims to tackle this issue through devolving current centralised control functionalities at DNO (Distributed Network Operator)'s control centre to a set of networked regional controllers deployed across the power distribution network to carry out either autonomous or cooperative control. In this paper, by taking voltage control as an example, we investigate the communication infrastructures to facilitate regional control in 11kV radial networks. Our study shows that current DNO's SCADA are inadequate to support efficient regional control due to structural and communication capability constraints which calls for new communication infrastructures.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123981426","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Fingerprint verification applying invariant moments 应用不变矩的指纹验证
2009 52nd IEEE International Midwest Symposium on Circuits and Systems Pub Date : 2009-09-15 DOI: 10.1109/MWSCAS.2009.5235878
J. Leon, G. Sanchez, G. Aguilar, L. Toscano, H. Pérez, J. M. Ramirez
{"title":"Fingerprint verification applying invariant moments","authors":"J. Leon, G. Sanchez, G. Aguilar, L. Toscano, H. Pérez, J. M. Ramirez","doi":"10.1109/MWSCAS.2009.5235878","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5235878","url":null,"abstract":"Traditional security systems use passwords or ID cards have been used to moderate access to restricted systems, but these kind of systems have a poor performance because the security can be easily breached. Based in this disadvantage, the biometrics systems have a great popularity, the mains biometrics systems are: face recognition, iris recognition, voice recognition, fingerprint recognition and sinning recognition. The fingerprint recognition is the oldest method used to recognition or verification of person. Our proposed a people recognition system with verification by invariant moments using two methodologies for the fingerprint enhancement. The goal in this work is to get a robust system in security issues. In this work a method for fingerprint verification is considered using a combination of Fast Fourier Transform (FFT) and Gabor Filters by image enhancement, both methods are first applied separately and later on an algebraic sum is done to obtain a single output. After that, a thinning algorithm is applied to get an image with the minimum thickness of 1 pixel. After this thinning algorithm, we apply an algorithm to look minutiae using a window of 3 by 3 pixels to scan the image. In this work we extract two types of minutiae, bifurcation and ending. Then, the feature vector is generated with the distance between minutiae, angle between minutiae and coordinates. In the recognition stage using the coordinates from the minutiae position on the image a comparison is done. After that, apply a verification stage using the invariant moments. With the invariant moments values a comparison is done. The comparison was done using the values obtained for the images into database and the test image for to get the output. The results obtained in this research are better when we used FFT and Gabor filters algorithms to image enhancement than we used separately.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125945895","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
A 3-GHz fully-integrated CMOS Class-AB power amplifier 3 ghz全集成CMOS ab类功率放大器
2009 52nd IEEE International Midwest Symposium on Circuits and Systems Pub Date : 2009-09-15 DOI: 10.1109/MWSCAS.2009.5235952
Y. Ng, L. Leung, K. Leung
{"title":"A 3-GHz fully-integrated CMOS Class-AB power amplifier","authors":"Y. Ng, L. Leung, K. Leung","doi":"10.1109/MWSCAS.2009.5235952","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5235952","url":null,"abstract":"A 3-GHz CMOS Class-AB power amplifier (PA) is presented in this paper. A two-stage cascode topology is used. All of the passive components including the drain inductors and load-pull output matching networks are integrated on the same chip to reduce the errors introduced to the output matching network and resonant tank in the driver. The circuit was fabricated in a 0.18-°m CMOS process. The measurement results show that the PA achieves a high power gain of 27.9 dB with saturated power of 20.6 dBm and power-added efficiency (PAE) of 12.7%. The PA was tested with IEEE 802.11a (WLAN) 54-Mbps and IEEE 802.16e (Mobile WiMAX) OFDM signals at 3-GHz. Error Vector Magnitudes (EVM) of −26.4 dB and −30.3 dB were measured, respectively. It is proved that the PA fulfils the requirements of both WLAN and WiMAX standards.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124743888","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Simplified 3.3V tolerance circuit for 2.5V I/O design in PCI-X signaling environment 简化3.3V容差电路，用于PCI-X信号环境下的2.5V I/O设计
2009 52nd IEEE International Midwest Symposium on Circuits and Systems Pub Date : 2009-09-15 DOI: 10.1109/MWSCAS.2009.5236049
Akshaykumar Salimath, S. Mandavilli
{"title":"Simplified 3.3V tolerance circuit for 2.5V I/O design in PCI-X signaling environment","authors":"Akshaykumar Salimath, S. Mandavilli","doi":"10.1109/MWSCAS.2009.5236049","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5236049","url":null,"abstract":"A low voltage interface circuit with a high voltage tolerance enables devices with different power supply levels to be efficiently coupled together without significant leakage current or damage to the circuits. The interface circuit includes an impedance control circuit, an output buffer, an input buffer, an isolation circuit and a pull up protection circuit. When a high voltage is applied to the IO pad, the pull-up protection circuit drives the gate of the pull up transistor to the high IO pad voltage to ensure that no current flows to the positive supply voltage. Also the isolation circuit couples the high IO pad voltage to the body of the pull-up transistor to prevent leakage current through parasitic diodes formed by the pull-up transistor.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"385 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124779895","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
High-speed transmitter for fully differential current-mode polyquaternary signaling scheme 用于全差分电流模式多元信令方案的高速发射机
2009 52nd IEEE International Midwest Symposium on Circuits and Systems Pub Date : 2009-09-15 DOI: 10.1109/MWSCAS.2009.5236148
S. Vijaya, M. Sharad, P. Mandal
{"title":"High-speed transmitter for fully differential current-mode polyquaternary signaling scheme","authors":"S. Vijaya, M. Sharad, P. Mandal","doi":"10.1109/MWSCAS.2009.5236148","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5236148","url":null,"abstract":"In this work we propose fully differential current-mode polyquaternary signaling transmitter for high-speed data transmission over chip-to-chip interconnect. Polyquaternary signaling is a bandwidth efficient signaling scheme suitable for bandwidth constrained and crosstalk prone chip-to-chip interconnect. Basic polyquaternary precoding scheme is adopted for symbol-by-symbol transmission which requires simple detection logic without increasing the precoding complexity. To achieve high-speed operation pipelining and parallel processing are incorporated in to the system building blocks without much increase of power. Polyquaternary filter is integrated within the current-mode driver to reduce power and area. All building blocks are realized in current-mode logic(CML). The circuits are implemented in 1.8-V, 0.18-µm digital CMOS process technology. The power consumed in the transmitter is 53.32-mW at the data transmission rate of 10-Gb/s over 20-cm FR4 PCB trace for the targeted bit error rate(BER) of 10−12","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124829638","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Current regenerative Schmitt triggers with tunable hysteresis 具有可调迟滞的电流再生施密特触发器
2009 52nd IEEE International Midwest Symposium on Circuits and Systems Pub Date : 2009-09-15 DOI: 10.1109/MWSCAS.2009.5236141
F. Yuan
{"title":"Current regenerative Schmitt triggers with tunable hysteresis","authors":"F. Yuan","doi":"10.1109/MWSCAS.2009.5236141","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5236141","url":null,"abstract":"A new current-regenerative Schmitt trigger is proposed and its characteristics are quantified both analytically and numerically. The center and width of the hysteresis of the proposed Schmitt trigger can be tuned. The low-impedance of the critical nodes of the Schmitt trigger enables it to operate at high frequencies. The proposed Schmitt trigger has been designed in TSMC-0.18µm 1.8V CMOS technology and analyzed using Spectre from Cadence Design Systems with BSIM3V3 device models. Simulation results are presented.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129417932","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A novel Farrow Structure with reduced complexity 一种降低复杂度的新颖的Farrow结构
2009 52nd IEEE International Midwest Symposium on Circuits and Systems Pub Date : 2009-09-15 DOI: 10.1109/MWSCAS.2009.5236027
M. Hunter, W. Mikhael
{"title":"A novel Farrow Structure with reduced complexity","authors":"M. Hunter, W. Mikhael","doi":"10.1109/MWSCAS.2009.5236027","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5236027","url":null,"abstract":"The Farrow Structure (FS) has become a standard for implementing polynomial-based interpolation filters. Several improvements have been made to enhance the performance and efficiency of the original structure. New structures have evolved from these developments. These new structures include the Modified Farrow Structure (MFS) and the Generalized Farrow Structure (GFS). The MFS takes advantage of linear phase, requiring approximately half the number of multiplications of the FS. The GFS employs oversampling to simplify the polynomial-based filter. In this contribution a novel Farrow Structure is derived. The new structure is termed the Generalized Modified Farrow Structure (GMFS). Also introduced is a special case of the GMFS, namely, the Dual Phase Modified Farrow Structure (DPMFS). It is shown that the DPMFS combines the advantages of both the GFS and MFS providing greater performance at reduced implementation cost.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129713506","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Mobility support for wireless sensor networks simulations for road intersection safety applications 道路交叉口安全应用无线传感器网络模拟的移动性支持
2009 52nd IEEE International Midwest Symposium on Circuits and Systems Pub Date : 2009-09-15 DOI: 10.1109/MWSCAS.2009.5236102
L. Hoehmann, A. Kummert
{"title":"Mobility support for wireless sensor networks simulations for road intersection safety applications","authors":"L. Hoehmann, A. Kummert","doi":"10.1109/MWSCAS.2009.5236102","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5236102","url":null,"abstract":"This paper provides a description of a system for collision detection of vehicles within a simulated wireless network scenario. One kind are wireless sensor networks, which collect environmental data and disseminate them over the network. Another application is the field of Car2Car communication, which will become more and more important in future. A network of nodes within a Car2Car scenario is characterized by high dynamics and road safety applications. In this work we present a new concept of combining a simulator for wireless sensor networks and a simulator of road traffic scenarios. Based on this new enhanced simulation environment we developed a first safety application which determines the trajectories of surrounding vehicles and estimates potential collisions.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129357697","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
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