An on-chip ramp generator for single-slope look ahead ramp (SSLAR) ADC

Abstract

An on-chip ramp generator was developed for single-slope look-ahead ramp (SSLAR) analog-to-digital converter (ADC) integrated in a column-parallel CMOS image sensor. Ramp generator is the central part of a new ADC algorithm which uses modified single-slope ramp (SSR) ADC timing. Ramp block designed such a way that it allows wide output voltage ranges as well as code hopping, code fall back and look-ahead operations in column-parallel ramp ADC. Ramp generator was fabricated using 0.5µm, 2P3M CMOS technology. Ramp generator composes of 10-bit synchronous counter, switched-capacitor based voltage steering circuits, output buffer and logic circuits. Effective layout area of ramp generator is 0.3mm2.