{"title":"片上斜坡发生器用于单斜坡前视斜坡(SSLAR) ADC","authors":"S. Balagopal, S. Ay","doi":"10.1109/MWSCAS.2009.5236076","DOIUrl":null,"url":null,"abstract":"An on-chip ramp generator was developed for single-slope look-ahead ramp (SSLAR) analog-to-digital converter (ADC) integrated in a column-parallel CMOS image sensor. Ramp generator is the central part of a new ADC algorithm which uses modified single-slope ramp (SSR) ADC timing. Ramp block designed such a way that it allows wide output voltage ranges as well as code hopping, code fall back and look-ahead operations in column-parallel ramp ADC. Ramp generator was fabricated using 0.5µm, 2P3M CMOS technology. Ramp generator composes of 10-bit synchronous counter, switched-capacitor based voltage steering circuits, output buffer and logic circuits. Effective layout area of ramp generator is 0.3mm2.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"173 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":"{\"title\":\"An on-chip ramp generator for single-slope look ahead ramp (SSLAR) ADC\",\"authors\":\"S. Balagopal, S. Ay\",\"doi\":\"10.1109/MWSCAS.2009.5236076\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"An on-chip ramp generator was developed for single-slope look-ahead ramp (SSLAR) analog-to-digital converter (ADC) integrated in a column-parallel CMOS image sensor. Ramp generator is the central part of a new ADC algorithm which uses modified single-slope ramp (SSR) ADC timing. Ramp block designed such a way that it allows wide output voltage ranges as well as code hopping, code fall back and look-ahead operations in column-parallel ramp ADC. Ramp generator was fabricated using 0.5µm, 2P3M CMOS technology. Ramp generator composes of 10-bit synchronous counter, switched-capacitor based voltage steering circuits, output buffer and logic circuits. Effective layout area of ramp generator is 0.3mm2.\",\"PeriodicalId\":254577,\"journal\":{\"name\":\"2009 52nd IEEE International Midwest Symposium on Circuits and Systems\",\"volume\":\"173 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2009-09-15\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"7\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2009 52nd IEEE International Midwest Symposium on Circuits and Systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/MWSCAS.2009.5236076\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MWSCAS.2009.5236076","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
An on-chip ramp generator for single-slope look ahead ramp (SSLAR) ADC
An on-chip ramp generator was developed for single-slope look-ahead ramp (SSLAR) analog-to-digital converter (ADC) integrated in a column-parallel CMOS image sensor. Ramp generator is the central part of a new ADC algorithm which uses modified single-slope ramp (SSR) ADC timing. Ramp block designed such a way that it allows wide output voltage ranges as well as code hopping, code fall back and look-ahead operations in column-parallel ramp ADC. Ramp generator was fabricated using 0.5µm, 2P3M CMOS technology. Ramp generator composes of 10-bit synchronous counter, switched-capacitor based voltage steering circuits, output buffer and logic circuits. Effective layout area of ramp generator is 0.3mm2.
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