Workshop on Memory Performance Issues最新文献_第2页

Memory coherence activity prediction in commercial workloads 商业工作负载中的内存一致性活动预测

Workshop on Memory Performance Issues Pub Date : 2004-06-20 DOI: 10.1145/1054943.1054949

Stephen Somogyi, T. Wenisch, N. Hardavellas, Jangwoo Kim, A. Ailamaki, B. Falsafi

引用次数: 41

Micro-architecture techniques in the intel® E8870 scalable memory controller 英特尔®E8870可扩展内存控制器中的微架构技术

Workshop on Memory Performance Issues Pub Date : 2004-06-20 DOI: 10.1145/1054943.1054948

F. Briggs, S. Chittor, Kai Cheng

引用次数: 7

On the effectiveness of prefetching and reuse in reducing L1 data cache traffic: a case study of Snort 关于预取和重用在减少L1数据缓存流量方面的有效性:Snort的案例研究

Workshop on Memory Performance Issues Pub Date : 2004-06-20 DOI: 10.1145/1054943.1054955

G. Surendra, Subhasish Banerjee, S. Nandy

引用次数: 1

Compiler-optimized usage of partitioned memories 分区内存的编译器优化使用

Workshop on Memory Performance Issues Pub Date : 2004-06-20 DOI: 10.1145/1054943.1054959

L. Wehmeyer, Urs Helmig, P. Marwedel

引用次数: 46

Understanding the effects of wrong-path memory references on processor performance 了解错误路径内存引用对处理器性能的影响

Workshop on Memory Performance Issues Pub Date : 2004-06-20 DOI: 10.1145/1054943.1054951

O. Mutlu, Hyesoon Kim, D. N. Armstrong, Y. Patt

{"title":"Understanding the effects of wrong-path memory references on processor performance","authors":"O. Mutlu, Hyesoon Kim, D. N. Armstrong, Y. Patt","doi":"10.1145/1054943.1054951","DOIUrl":"https://doi.org/10.1145/1054943.1054951","url":null,"abstract":"High-performance out-of-order processors spend a significant portion of their execution time on the incorrect program path even though they employ aggressive branch prediction algorithms. Although memory references generated on the wrong path do not change the architectural state of the processor, they can affect the arrangement of data in the memory hierarchy. This paper examines the effects of wrong-path memory references on processor performance. It is shown that these references significantly affect the IPC (Instructions Per Cycle) performance of a processor. Not modeling them can lead to errors of up to 10% in IPC estimates for the SPEC2000 integer benchmarks; 7 out of 12 benchmarks experience an error of greater than 2% in IPC estimates. In general, the error in the IPC increases with increasing memory latency and instruction window size.We find that wrong-path references are usually beneficial for performance, because they prefetch data that will be used by later correct-path references. L2 cache pollution is found to be the most significant negative effect of wrong-path references. Code examples are shown to provide insights into how wrong-path references affect performance.","PeriodicalId":249099,"journal":{"name":"Workshop on Memory Performance Issues","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131748325","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 27

A case for multi-level main memory 多级主存储器的一个实例

Workshop on Memory Performance Issues Pub Date : 2004-06-20 DOI: 10.1145/1054943.1054944

M. Ekman, P. Stenström

引用次数: 18

Evaluating kilo-instruction multiprocessors 求千指令多处理器

Workshop on Memory Performance Issues Pub Date : 2004-06-20 DOI: 10.1145/1054943.1054953

M. Galluzzi, R. Beivide, Valentin Puente, J. Gregorio, A. Cristal, M. Valero

{"title":"Evaluating kilo-instruction multiprocessors","authors":"M. Galluzzi, R. Beivide, Valentin Puente, J. Gregorio, A. Cristal, M. Valero","doi":"10.1145/1054943.1054953","DOIUrl":"https://doi.org/10.1145/1054943.1054953","url":null,"abstract":"The ever increasing gap in processor and memory speeds has a very negative impact on performance. One possible solution to overcome this problem is the Kilo-instruction processor. It is a recent proposed architecture able to hide large memory latencies by having thousands of in-flight instructions. Current multiprocessor systems also have to deal with this increasing memory latency while facing other sources of latencies: those coming from communication among processors. What we propose, in this paper, is the use of Kilo-instruction processors as computing nodes for small-scale CCNUMA multiprocessors. We evaluate what we appropriately call Kilo-instruction Multiprocessors. This kind of systems appears to achieve very good performance while showing two interesting behaviours. First, the great amount of in-flight instructions makes the system not just to hide the latencies coming from the memory accesses but also the inherent communication latencies involved in remote memory accesses. Second, the significant pressure imposed by many in-flight instructions translates into a very high contention for the interconnection network, what indicates us that more efforts need to be employed in designing routers capable of managing high traffic levels.","PeriodicalId":249099,"journal":{"name":"Workshop on Memory Performance Issues","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122634974","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

A low-power memory hierarchy for a fully programmable baseband processor 用于完全可编程基带处理器的低功耗存储器层次结构

Workshop on Memory Performance Issues Pub Date : 2004-06-20 DOI: 10.1145/1054943.1054957

W. Raab, Hans-Martin Blüthgen, U. Ramacher

引用次数: 5