2017 75th Annual Device Research Conference (DRC)最新文献_第8页

Double bilayer graphene-WSe2 resonant tunneling heterostructures with high interlayer current densities and peak-to-valley ratios 具有高层间电流密度和峰谷比的双双层石墨烯- wse2共振隧道异质结构

2017 75th Annual Device Research Conference (DRC) Pub Date : 2017-06-01 DOI: 10.1109/DRC.2017.7999393

G. William Burg, B. Fallahazad, K. Kim, N. Prasad, T. Taniguchi, Kenji Watanabe, L. F. Register, E. Tutuc

引用次数: 0

Al0.45Ga0.55N/Al0.30Ga0.70N high electron mobility transistors with Schottky gates and small subthreshold slope factor Al0.45Ga0.55N/Al0.30Ga0.70N高电子迁移率晶体管，具有肖特基栅极和小亚阈值斜率因子

2017 75th Annual Device Research Conference (DRC) Pub Date : 2017-06-01 DOI: 10.1109/DRC.2017.7999448

A. Baca, A. Armstrong, A. Allerman, B. Klein, E. Douglas, C. Sanchez, T. Fortune

引用次数: 0

Novel fabrication method and structure of single crystal thin film In0.53Ga0.47As Schottky diodes for potential IR applications 具有潜在红外应用前景的单晶薄膜In0.53Ga0.47As肖特基二极管的新制备方法和结构

2017 75th Annual Device Research Conference (DRC) Pub Date : 2017-06-01 DOI: 10.1109/DRC.2017.7999441

R. Hussin, Yi Luo

引用次数: 0

Self-aligned ZnO thin-film transistors with 860 MHz fT and 2 GHz fmax for large-area applications 自对准ZnO薄膜晶体管，860mhz fT和2ghz fmax用于大面积应用

2017 75th Annual Device Research Conference (DRC) Pub Date : 2017-06-01 DOI: 10.1109/DRC.2017.7999510

Yoni Mehlman, Y. Afsar, Naveen Yerma, S. Wagner, J. Sturm

引用次数: 14

Suspended ReSi FET for improved photocurrent-time response 悬挂式ReSi场效应管，改善了光电时间响应

2017 75th Annual Device Research Conference (DRC) Pub Date : 2017-06-01 DOI: 10.1109/DRC.2017.7999439

Bablu Mukherjee, Kartikey Thakar, Naveen Kaushik, S. Lodha

引用次数: 2

Self-aligned contact metallization to AlGaN/GaN heterostructures AlGaN/GaN异质结构的自对准接触金属化

2017 75th Annual Device Research Conference (DRC) Pub Date : 2017-06-01 DOI: 10.1109/DRC.2017.7999449

Derek W. Johnson, M. Babb, Pradhyumna Ravikirthi, J. Suh, H. Harris

引用次数: 0

Towards electro-optical integration of hybrid III-V on Si lasers into the BEOL of a CMOS technology 在CMOS技术的BEOL中实现混合III-V - Si激光器的电光集成

2017 75th Annual Device Research Conference (DRC) Pub Date : 2017-06-01 DOI: 10.1109/DRC.2017.7999518

H. Hahn, M. Seifried, G. Villares, Y. Baumgartner, M. Halter, C. Caër, D. Caimi, M. Sousa, R. Dangel, N. Meier, F. Horst, L. Czornomaz, B. Offrein

{"title":"Towards electro-optical integration of hybrid III-V on Si lasers into the BEOL of a CMOS technology","authors":"H. Hahn, M. Seifried, G. Villares, Y. Baumgartner, M. Halter, C. Caër, D. Caimi, M. Sousa, R. Dangel, N. Meier, F. Horst, L. Czornomaz, B. Offrein","doi":"10.1109/DRC.2017.7999518","DOIUrl":"https://doi.org/10.1109/DRC.2017.7999518","url":null,"abstract":"Interconnects have become a severe bottleneck in today's computing hardware [1]. For large-scale data centers in particular, the interconnect situation is even more severe [2]. The interconnect bandwidth and bandwidth density have to be increased on all system-levels. The ideal technology to increase the density is Si photonics (SiPh). While the integration of most of the SiPh components has been mastered already on a 90 nm CMOS platform [3], the integration of III-V materials to yield directly-modulated lasers still poses a major challenge. This integration is considered as the cornerstone for reaching a complete, yet cost-competitive, SiPh-CMOS marriage. Most concepts shown so far [4, 5] either lack CMOS-compatibility or have device dimensions that hinder the integration of the laser into a standard BEOL. To allow for a common BEOL between SiPh and CMOS, we integrate the III-V material between the FEOL and BEOL, within the first interlayer dielectric ILD0' (Fig. 1). Such integration imposes tight requirements on device dimensions as well as several technological challenges that have to be mastered. We report here on decisive aspects of such integration. This represents a major step towards a full integration of III-V, SiPh and CMOS.","PeriodicalId":248087,"journal":{"name":"2017 75th Annual Device Research Conference (DRC)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125708521","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

A high-current InP-channel triple heterojunction tunnel transistor design 一种大电流inp沟道三异质结隧道晶体管设计

2017 75th Annual Device Research Conference (DRC) Pub Date : 2017-06-01 DOI: 10.1109/DRC.2017.7999437

P. Long, M. Povolotskyi, Jun Z. Huang, J. Charles, T. Kubis, Gerhard Klimeck, M. Rodwell

{"title":"A high-current InP-channel triple heterojunction tunnel transistor design","authors":"P. Long, M. Povolotskyi, Jun Z. Huang, J. Charles, T. Kubis, Gerhard Klimeck, M. Rodwell","doi":"10.1109/DRC.2017.7999437","DOIUrl":"https://doi.org/10.1109/DRC.2017.7999437","url":null,"abstract":"VLSI devices are constrained by CF<inf>dd</inf><sup>2</sup>/2 power dissipation. Low power dissipation requires low V<inf>dd</inf>, yet reducing V<inf>dd</inf> increases I<inf>off</inf>. Tunnel FETs (TFETs) have steep subthreshold swings (S.S.) and can operate at low V<inf>dd</inf>, yet their I<inf>on</inf> is limited by low tunneling probability. This low I<inf>on</inf> results in large CV<inf>dd</inf>/I delay and slow logic operation. For greatly increased Ion, we had proposed a triple-heterojunction (3HJ) TFET design incorporating source and channel heterojunctions (HJ) [1, 2]. The designs of [1, 2] have an InAlAsSb channel, yet no low-trap-density dielectric interfaces to InAlAsSb have been reported. In contrast, low-trap-density dielectric interfaces have been demonstrated to InAs, InGaAs, and InP [3, 4, 5]. Here we propose an InGaAs/GaAsSb/InAs/InP 3HJ TFET design, with growth lattice-matched to InP. The gated channel surface is InAs and InP, and thus can have low trap density. The p-type side of the tunnel junction is GaAsSb, instead of strained GaSb [6], as compressive strain increases the hole transport effective mass, reducing the tunneling probability. In ballistic simulations, with I<inf>off</inf>= 10 <sup>3</sup> μA/μm and V<inf>dd</inf>=0.3V, I<inf>on</inf> is an extremely high 540μA/μm. Even when simulated assuming incoherent quantum transport, with acoustic and optical phonon scattering modelled, I<inf>on</inf> remains very high at 250μA/μm.","PeriodicalId":248087,"journal":{"name":"2017 75th Annual Device Research Conference (DRC)","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128418962","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Flash memory TFT based on fully solution processed oxide 基于全溶液处理氧化物的TFT闪存

2017 75th Annual Device Research Conference (DRC) Pub Date : 2017-06-01 DOI: 10.1109/DRC.2017.7999508

Sandip Mondai, V. Venkataraman

{"title":"Flash memory TFT based on fully solution processed oxide","authors":"Sandip Mondai, V. Venkataraman","doi":"10.1109/DRC.2017.7999508","DOIUrl":"https://doi.org/10.1109/DRC.2017.7999508","url":null,"abstract":"Charge trapping based non-volatile capacitive flash memory has taken a significant share of today's semiconductor electronics[1]-[3]. As of now, there is no alternative to Silicon Nitride (Sis N4) dielectric for memory technology in terms of low-leakage and intrinsic charge storage properties. However the fabrication process of Si3N4 memory device is very complicated and requires sophisticated ultra-high vacuum system, which is incompatible towards building system on panel (SOP), system on glass (SOG) or ‘see through’ display technologies for large area and cost effective electronics applications[4]. Therefore it is necessary to develop fully spin-coated, sol-gel processed, cost effective flash memory TFT. Recently we reported a fully solution processed two terminal capacitive memory device [3]. However such devices are not suitable for large arrays since flash memory technology today relies on three terminal memory TFTs which are more superior in terms of readout and integration. Here we demonstrate all inorganic, completely oxide based, robust, cost-effective, fully solution processed spin-coated Silicon-Oxide-Hafnia-oxide-Semiconductor (SOHOS) flash memory devices. The performance of fully sol-gel processed memory TFT is equivalent or better than similar devices fabricated by other techniques. We also demonstrate the memory operation mechanism of the device using the experimentally determined complete band structure.","PeriodicalId":248087,"journal":{"name":"2017 75th Annual Device Research Conference (DRC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130630415","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Plasmonic enhanced polarization sensitive black phosphorus photodetection device 等离子体增强极化灵敏黑磷光探测装置

2017 75th Annual Device Research Conference (DRC) Pub Date : 2017-06-01 DOI: 10.1109/DRC.2017.7999440

Yexin Deng, Prabhu K. Venuthurumilli, Zhe Luo, N. Conrad, Xianfan Xu, P. Ye

引用次数: 0