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High-performance nanoscale topological inductor 高性能纳米级拓扑电感
2017 75th Annual Device Research Conference (DRC) Pub Date : 2017-06-01 DOI: 10.1109/DRC.2017.7999424
Timothy M. Philip, M. Gilbert
{"title":"High-performance nanoscale topological inductor","authors":"Timothy M. Philip, M. Gilbert","doi":"10.1109/DRC.2017.7999424","DOIUrl":"https://doi.org/10.1109/DRC.2017.7999424","url":null,"abstract":"Despite being an important constituent of a variety of RF and voltage regulating circuits, on-chip inductors have failed to scale at the same rapid pace as other components such as capacitors and transistors. This failure is largely due to the bulky spiral geometry that is needed for planar device fabrication, which results in low inductance densities. Ultimately, an alternative design paradigm using new phenomena and materials is necessary to achieve the miniaturization and performance goals for the future of these vital components. Here, we present a novel inductor design that achieves high performance by utilizing the surface states of 3D time-reversal-invariant (TRI) topological insulators (TIs).","PeriodicalId":248087,"journal":{"name":"2017 75th Annual Device Research Conference (DRC)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133120909","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Narrow line crystallization of rubrene thin film enhanced by Yb interfacial layer for single crystal OFET application Yb界面层增强橡胶薄膜窄线结晶，用于单晶OFET
2017 75th Annual Device Research Conference (DRC) Pub Date : 2017-06-01 DOI: 10.1109/DRC.2017.7999464
S. Ohmi, M. Hiroki, Y. Maeda
{"title":"Narrow line crystallization of rubrene thin film enhanced by Yb interfacial layer for single crystal OFET application","authors":"S. Ohmi, M. Hiroki, Y. Maeda","doi":"10.1109/DRC.2017.7999464","DOIUrl":"https://doi.org/10.1109/DRC.2017.7999464","url":null,"abstract":"Rubrene is one of the most promising organic semiconductor for OFET application. The high hole mobility such 1.21 cm2/(Vs) has been reported for the OFET with rubrene thin film evaporated on SiO2 gate insulator for bottom-g; geometry [1]. However, the crystallization of rubrene thin film on SiO2 is difficult to be controlled. A self-assembled monolayer (SAM) scheme is often used to realize the good crystallinigy of organic semiconductor films. However, it 1 an issue in terms of the uniformity which would be an issue of large scale integration of OFETs. In this paper, we ha investigated the narrow line crystallization of rubrene thin film utilizing Yb interfacial layer, which is able to be in-s deposited in a same chamber for rubrene deposition, for the first time.","PeriodicalId":248087,"journal":{"name":"2017 75th Annual Device Research Conference (DRC)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123427611","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A non-volatile cascadable magneto-electric material implication logic 一种非易失性级联磁电材料隐含逻辑
2017 75th Annual Device Research Conference (DRC) Pub Date : 2017-06-01 DOI: 10.1109/DRC.2017.7999434
Akhilesh R. Jaiswal, I. Chakraborty, K. Roy
{"title":"A non-volatile cascadable magneto-electric material implication logic","authors":"Akhilesh R. Jaiswal, I. Chakraborty, K. Roy","doi":"10.1109/DRC.2017.7999434","DOIUrl":"https://doi.org/10.1109/DRC.2017.7999434","url":null,"abstract":"Shannon's seminal work on Boolean operators — AND, OR, NOT has been the backbone of on-chip digital logic design. This set of the so called basic gates excludes an important mathematical logical operator — the Material Implication (IMP) logic (and its complement (NIMP)), shown in Fig. 1(a). IMP gate along with a NOT/XOR/NIMP gate forms a complete logic basis. Moreover, including IMP as a basic gate along with AND, OR, NOT allows better logic optimization. In this paper, we propose a non-volatile IMP (NIMP) gate that can be seamlessly cascaded to implement complex Boolean functions. Our work differs from previous works as in [1], which used crossbars for implementing IMP logic. Unlike crossbars, our proposed gates can be cascaded and used for standard logic computations or optimization.","PeriodicalId":248087,"journal":{"name":"2017 75th Annual Device Research Conference (DRC)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127939066","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Multilayer silicon nitride-on-silicon photonic platforms for three-dimensional integrated photonic devices and circuits 用于三维集成光子器件和电路的多层氮化硅光子平台
2017 75th Annual Device Research Conference (DRC) Pub Date : 2017-06-01 DOI: 10.1109/DRC.2017.7999502
J. Poon, W. Sacher
{"title":"Multilayer silicon nitride-on-silicon photonic platforms for three-dimensional integrated photonic devices and circuits","authors":"J. Poon, W. Sacher","doi":"10.1109/DRC.2017.7999502","DOIUrl":"https://doi.org/10.1109/DRC.2017.7999502","url":null,"abstract":"Today, generic foundry silicon photonic platforms use only one waveguide layer, implemented in the top silicon (Si) device layer of a silicon-on-insulator (SOI) wafer. However, very large-scale integrated photonic circuits. comprising of hundreds or even thousands of devices, require complex on-chip optical routing networks that become difficult or impractical to implement using only one Si waveguide layer because of waveguide crossing loss, crossing crosstalk, optical power handling limitations, and/or waveguide loss. Such very large-scale integrated photonic circuits enable applications in, for example, optical switch fabrics and optical phased arrays. Integrated photonic platforms that have several waveguide layers make possible three-dimensional (3D) on-chip optical routing to overcome the limitations of a single layer. For example, multilayer platforms support extraordinarily low loss over/under-pass types of crossings, wherein a waveguide in the topmost (bottommost) layer can pass over (under) many waveguides in the lower (upper) levels.","PeriodicalId":248087,"journal":{"name":"2017 75th Annual Device Research Conference (DRC)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121422418","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
The device research conference: 1992–2017 and 2017–2042 设备研究会议:1992-2017年和2017-2042年
2017 75th Annual Device Research Conference (DRC) Pub Date : 2017-06-01 DOI: 10.1109/DRC.2017.7999473
M. Rodwell
{"title":"The device research conference: 1992–2017 and 2017–2042","authors":"M. Rodwell","doi":"10.1109/DRC.2017.7999473","DOIUrl":"https://doi.org/10.1109/DRC.2017.7999473","url":null,"abstract":"Starting with its 50th anniversary in 1992, I have seen 25 years of electron and photon device research at the DRC; let us look over this history and then guess at the future.","PeriodicalId":248087,"journal":{"name":"2017 75th Annual Device Research Conference (DRC)","volume":"2019 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121453389","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Your golden age of device research 你们设备研究的黄金时代
2017 75th Annual Device Research Conference (DRC) Pub Date : 2017-06-01 DOI: 10.1109/DRC.2017.7999471
T. N. Jackson
{"title":"Your golden age of device research","authors":"T. N. Jackson","doi":"10.1109/DRC.2017.7999471","DOIUrl":"https://doi.org/10.1109/DRC.2017.7999471","url":null,"abstract":"Twenty-five years ago I had the honor of serving as technical program chair for the 50th Device Research Conference. For the plenary session we invited grey beards: Chapin Cutler, Makoto Kikuchi, Jim Early, and Herb Kroemer. I enjoyed the talks and after the session a young attendee remarked how great it must have been to be involved in the device research the plenary speakers recounted. I agreed that the grey beards had done great work, but noted that if I had been doing device research then I might have been too witless to see BJTs through the lens of the point contact transistor, too lazy to bring the junction laser to practical utility, too slow to see heterojunctions everywhere. After all, there were a lot of old device researchers not giving plenary talks and many companies had come and gone. I also noted that I had had a lot of fun working on devices in more recent times, and that I greatly preferred the parameter analyzer and electron microscopes I used to the curve tracers and worse of my predecessors. I've had the pleasure of participating in every DRC but one since 1979 (the one due to the birth of my younger son), with, if I have counted correctly, 44 talks from myself or my students, including some firsts or bests such as ultra-short-gate-length self-aligned GaAs MESFETs, superconducting JFETs, Ge MOSFETs, high mobility organic (pentacene) TFTs, flexible electronics demos, fast oxide semiconductor devices, and more.","PeriodicalId":248087,"journal":{"name":"2017 75th Annual Device Research Conference (DRC)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117223718","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Scaling challenges of FinFET architecture below 40nm contacted gate pitch 40nm接触栅极间距以下FinFET架构的缩放挑战
2017 75th Annual Device Research Conference (DRC) Pub Date : 2017-06-01 DOI: 10.1109/DRC.2017.7999495
A. Razavieh, P. Zeitzoff, D. Brown, G. Karve, E. Nowak
{"title":"Scaling challenges of FinFET architecture below 40nm contacted gate pitch","authors":"A. Razavieh, P. Zeitzoff, D. Brown, G. Karve, E. Nowak","doi":"10.1109/DRC.2017.7999495","DOIUrl":"https://doi.org/10.1109/DRC.2017.7999495","url":null,"abstract":"The FinFET architecture, introduced at the 22nm node [1], has delivered improved MOSFET electrostatics, which has enabled gate-length (L<inf>Gate</inf>) scaling down to 48nm Contacted Gate Pitch (CPP) at the 7nm node [2], [3] (Fig. 1). Enhanced performance gains have been realized via the ‘Fin Effect’ (W<inf>eff</inf>/Fin-Pitch) boost, which provides improved drive current for a given capacitive load. However, limits on the Fin thickness are quickly being approached and will soon limit further L<inf>Gate</inf> scaling, resulting in accelerated reduction in source/drain sizes vs. CPP. The combination of increasing Fin Effect and a plateau in the L<inf>Gate</inf> place extreme pressure on the vertical conduction path from contacts to source and drain. With current values of contact resistivity (pc) for metal-to-degenerately-doped silicon of ∼2×10<sup>−9</sup> [4] FinFET performance will significantly deteriorate below CPP of ∼40nm, while a theoretical fully ohmic floor of ∼1×10<sup>−10</sup>Ω-cm<sup>2</sup> [5] could push the CPP limit to below 30nm. We conclude that there will be severe pressure for the industry to adopt a new device architecture or scaling option in the 30–40nm CPP region to carry on the power/performance benefits of CMOS scaling.","PeriodicalId":248087,"journal":{"name":"2017 75th Annual Device Research Conference (DRC)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132508406","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Gallium selenide (GaSe)-molybdenum disulfide (MOS2) van der Waals heterojunction diodes 硒化镓(GaSe)-二硫化钼(MOS2)范德华异质结二极管
2017 75th Annual Device Research Conference (DRC) Pub Date : 2017-06-01 DOI: 10.1109/DRC.2017.7999419
Arnob Islam, Jaesung Lee, P. Feng
{"title":"Gallium selenide (GaSe)-molybdenum disulfide (MOS2) van der Waals heterojunction diodes","authors":"Arnob Islam, Jaesung Lee, P. Feng","doi":"10.1109/DRC.2017.7999419","DOIUrl":"https://doi.org/10.1109/DRC.2017.7999419","url":null,"abstract":"van der Waals (vdW) heterostructures enabled by two-dimensional (2D) semimetals and semiconductors [1] have shown interesting attractions and great promises toward realizing future-generation high performance electronic and optoelectronic devices. In this study, we demonstrate gallium selenide (GaSe) (p-type) /molybdenum disulfide (MoS2) (n-type) heterojunction. This heterojunction shows p-n junction diode behavior with good rectification ratio of ∼103 at zero gate voltage. In addition, it shows gate tunable behavior with n-type characteristics. Furthermore, we characterize photoresponse of the device under 532 nm laser illumination and obtain photoresponsivity of ∼71 mA/W.","PeriodicalId":248087,"journal":{"name":"2017 75th Annual Device Research Conference (DRC)","volume":"23 5","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114043740","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
First InGaAs lateral nanowire MOSFET RF noise measurements and model 第一InGaAs横向纳米线MOSFET射频噪声测量和模型
2017 75th Annual Device Research Conference (DRC) Pub Date : 2017-06-01 DOI: 10.1109/DRC.2017.7999451
L. Ohlsson, F. Lindelöw, C. Zota, M. Ohlrogge, T. Merkle, L. Wernersson, E. Lind
{"title":"First InGaAs lateral nanowire MOSFET RF noise measurements and model","authors":"L. Ohlsson, F. Lindelöw, C. Zota, M. Ohlrogge, T. Merkle, L. Wernersson, E. Lind","doi":"10.1109/DRC.2017.7999451","DOIUrl":"https://doi.org/10.1109/DRC.2017.7999451","url":null,"abstract":"The first radio frequency (RF) noise measurements on lateral nanowire metal-oxide-semiconductor field-effect transistors (MOSFETs) and a noise model are presented. We have characterized the RF noise and scattering parameters of an indium gallium arsenide (InGaAs) device. A fitted model yields extrapolated ft = 316 GHz current gain cutoff and fmax = 166 GHz maximum oscillation frequency. This device technology is being developed for millimeter wave circuit implementations, targeting a 94 GHz carrier frequency. The modeled intrinsic Fmin < 1dB minimum noise figure obtained promises performance at the target band, given reduction of gate parasitics. In any wireless system, noise and bandwidth limits the performance. Understanding of RF noise in nanowire MOSFET devices is thereby key for realization of future radar and communications systems.","PeriodicalId":248087,"journal":{"name":"2017 75th Annual Device Research Conference (DRC)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114160454","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Glucose sensing using dual-gated BioFETs with 5nm-thick silicon body 采用5nm厚硅体的双门控生物场效应管进行葡萄糖传感
2017 75th Annual Device Research Conference (DRC) Pub Date : 2017-06-01 DOI: 10.1109/DRC.2017.7999421
Ting Wu, A. Afzali, Kae-Dyi You, K. Kisslinger, E. Stach, D. Shahrjerdi
{"title":"Glucose sensing using dual-gated BioFETs with 5nm-thick silicon body","authors":"Ting Wu, A. Afzali, Kae-Dyi You, K. Kisslinger, E. Stach, D. Shahrjerdi","doi":"10.1109/DRC.2017.7999421","DOIUrl":"https://doi.org/10.1109/DRC.2017.7999421","url":null,"abstract":"Field-effect transistors (FETs) are commonly used as affinity-based electrical transducers, known as bioFETs. These sensors are, however, unable to directly detect uncharged molecules such as glucose, necessitating the use of ligand molecules. Further, the change of the electrical signal resulting from the biochemical reactions is often small. In the past decade, significant research was done to enhance the sensitivity of bioFETs using nanowire1 and nanoribbon structures. Recently, dual-gated bioFETs were also shown to exceed the Nernst limit of 59mV/pH using capacitive coupling3,4. Here, we introduce a new ligand molecule for the direct detection of glucose using bioFETs. We demonstrate the amplification of the electrical signal originating from the glucose reaction using our “engineered” dual-gated bioFETs featuring ultra-thin silicon body and buried oxide of 5nm and 10nm, respectively.","PeriodicalId":248087,"journal":{"name":"2017 75th Annual Device Research Conference (DRC)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124090168","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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