High-performance nanoscale topological inductor

Timothy M. Philip, M. Gilbert
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引用次数: 2

Abstract

Despite being an important constituent of a variety of RF and voltage regulating circuits, on-chip inductors have failed to scale at the same rapid pace as other components such as capacitors and transistors. This failure is largely due to the bulky spiral geometry that is needed for planar device fabrication, which results in low inductance densities. Ultimately, an alternative design paradigm using new phenomena and materials is necessary to achieve the miniaturization and performance goals for the future of these vital components. Here, we present a novel inductor design that achieves high performance by utilizing the surface states of 3D time-reversal-invariant (TRI) topological insulators (TIs).
高性能纳米级拓扑电感
尽管片上电感是各种射频和电压调节电路的重要组成部分,但它未能像电容器和晶体管等其他元件那样快速扩展。这种失败主要是由于平面器件制造所需的笨重的螺旋几何结构,导致电感密度低。最终,使用新现象和新材料的替代设计范式是实现这些重要部件未来的小型化和性能目标所必需的。在这里,我们提出了一种新的电感设计,通过利用三维时间逆不变(TRI)拓扑绝缘体(TIs)的表面状态来实现高性能。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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