2012 IEEE 18th International On-Line Testing Symposium (IOLTS)最新文献

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Logic masking for SET Mitigation Using Approximate Logic Circuits 使用近似逻辑电路的SET抑制逻辑屏蔽
2012 IEEE 18th International On-Line Testing Symposium (IOLTS) Pub Date : 2012-06-27 DOI: 10.1109/IOLTS.2012.6313868
A. Sánchez-Clemente, L. Entrena, M. García-Valderas, C. López-Ongil
{"title":"Logic masking for SET Mitigation Using Approximate Logic Circuits","authors":"A. Sánchez-Clemente, L. Entrena, M. García-Valderas, C. López-Ongil","doi":"10.1109/IOLTS.2012.6313868","DOIUrl":"https://doi.org/10.1109/IOLTS.2012.6313868","url":null,"abstract":"Logic masking approaches for Single-Event Transient (SET) mitigation use hardware redundancy to mask the propagation of SET effects. Conventional techniques, such as Triple-Modular Redundancy (TMR), can guarantee full fault coverage, but they also introduce very large overheads. Alternatively, approximate logic circuits can provide the necessary flexibility to find an optimal balance between error coverage and overheads. In this work, we propose a new approach to build approximate logic circuits driven by testability estimations. Using the concept of unate functions, approximations are performed in lines with low testability in order to minimize the impact on error coverage. The proposed approach is scalable and can provide a variety of solutions for different trade-offs between error coverage and overheads.","PeriodicalId":246222,"journal":{"name":"2012 IEEE 18th International On-Line Testing Symposium (IOLTS)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127949100","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 34
Reliable and secure memories based on algebraic manipulation correction codes 基于代数操作校正码的可靠和安全的存储器
2012 IEEE 18th International On-Line Testing Symposium (IOLTS) Pub Date : 2012-06-27 DOI: 10.1109/IOLTS.2012.6313861
Zhen Wang, M. Karpovsky
{"title":"Reliable and secure memories based on algebraic manipulation correction codes","authors":"Zhen Wang, M. Karpovsky","doi":"10.1109/IOLTS.2012.6313861","DOIUrl":"https://doi.org/10.1109/IOLTS.2012.6313861","url":null,"abstract":"The reliability and security of memories are crucial considerations in the modern digital system design. Traditional codes usually concentrate on detecting and correcting errors of certain types, e.g. errors with small multiplicities or byte errors, and cannot detect or correct unanticipated errors. In this paper we present a reliable and secure memory architecture based on robust Algebraic Manipulation Correction codes. These codes can provide a guaranteed error detection probability and can correct any error regardless of its multiplicity as long as the error stays for several consecutive clock cycles. The construction and the error correction procedure for the code will be described. The probability that an error can be successfully detected and/or corrected and the hardware overhead of the memory architecture based on these codes will be estimated.","PeriodicalId":246222,"journal":{"name":"2012 IEEE 18th International On-Line Testing Symposium (IOLTS)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116993018","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
A real-case application of a synergetic design-flow-oriented SER analysis 协同设计流导向SER分析的实际应用
2012 IEEE 18th International On-Line Testing Symposium (IOLTS) Pub Date : 2012-06-27 DOI: 10.1109/IOLTS.2012.6313839
M. Vilchis, R. Venkatraman, Enrico Costenaro, D. Alexandrescu
{"title":"A real-case application of a synergetic design-flow-oriented SER analysis","authors":"M. Vilchis, R. Venkatraman, Enrico Costenaro, D. Alexandrescu","doi":"10.1109/IOLTS.2012.6313839","DOIUrl":"https://doi.org/10.1109/IOLTS.2012.6313839","url":null,"abstract":"We present a methodology that investigates SEEs in complex SOCs. The analysis integrates tightly with the design flow and provides static and dynamic de-rating algorithms. This approach is in good agreement with alpha testing results obtained from a 40nm CMOS testchip with sixty-four independently controlled/selectable Advanced Encryption Standard (AES) based processing element (PE) blocks.","PeriodicalId":246222,"journal":{"name":"2012 IEEE 18th International On-Line Testing Symposium (IOLTS)","volume":"147 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116400524","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Cross-level protection of circuits against faults and malicious attacks 防止电路故障和恶意攻击的跨级保护
2012 IEEE 18th International On-Line Testing Symposium (IOLTS) Pub Date : 2012-06-27 DOI: 10.1109/IOLTS.2012.6313862
V. Tomashevich, S. Srinivasan, Fabian Foerg, I. Polian
{"title":"Cross-level protection of circuits against faults and malicious attacks","authors":"V. Tomashevich, S. Srinivasan, Fabian Foerg, I. Polian","doi":"10.1109/IOLTS.2012.6313862","DOIUrl":"https://doi.org/10.1109/IOLTS.2012.6313862","url":null,"abstract":"Nanoscale electronics is increasingly affected by disturbances caused by radiation, noise and effects of statistical process variations. Moreover, deliberate injection of faults into cryptographic circuits is used by malicious attackers to perform cryptanalysis and gain access to sensitive information. Error-detecting codes are employed to protect circuits against such disturbances, and new advanced codes specifically designed to counter malicious attacks have recently been introduced. However, a number of logic gates in the circuit are not adequately protected by the error-detecting code, as faults affecting these gates escape detection with a relatively high probability. We introduce a cross-level protection solution, where a light-weight error-detecting code is combined with hardening of insufficiently protected gates using transistor resizing. Such gates are determined by FPGA-supported fault injection. A thorough electrical analysis is performed in order to modify the electrical parameters of these gates such that faults are highly unlikely. We report area and power overhead for a number of error-detecting codes. To the best of our knowledge, this is the first work which co-optimizes fault handling by information redundancy based on error-detecting codes and by hardening individual circuit elements.","PeriodicalId":246222,"journal":{"name":"2012 IEEE 18th International On-Line Testing Symposium (IOLTS)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124164723","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
Event-driven on-line co-simulation with fault diagnostic 带有故障诊断的事件驱动在线联合仿真
2012 IEEE 18th International On-Line Testing Symposium (IOLTS) Pub Date : 2012-06-27 DOI: 10.1109/IOLTS.2012.6313854
M. Baklashov
{"title":"Event-driven on-line co-simulation with fault diagnostic","authors":"M. Baklashov","doi":"10.1109/IOLTS.2012.6313854","DOIUrl":"https://doi.org/10.1109/IOLTS.2012.6313854","url":null,"abstract":"This paper introduces a functional co-validation technique realized inside co-simulation methodology, environment and tool. On-line co-simulation intends to concurrently simulate an execution of original binary applications and their binary translated images. Both, original and translated instructions execute under an Instruction Set Simulator (ISS) in a Virtual System Prototyping Environment (VSPE) that models hardware platform or chipset targeted to a given Instruction Set Architecture (ISA). Real world applications accounting for billions of instructions executing in VSPE under Operating System (OS) control may exhibit hard to reproduce and debug fatal failures. When dealing with such enormous state space, co-validation becomes a critical factor under tight schedules of the software/hardware co-design. The paper presents a mathematical model that allows for abstracting the huge co-simulated state space and special events of interest. A fault diagnostic mode implemented inside the tool couples run time software exception handling mechanisms with the events thus accommodating application runs to runtime failures for further debugging guidance. The tool implemented in C++ runs seamlessly inside VSPE.","PeriodicalId":246222,"journal":{"name":"2012 IEEE 18th International On-Line Testing Symposium (IOLTS)","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133711832","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Pilot symbol driven monitoring of electrical degradation in RF transmitter systems using model anomaly diagnosis 基于模型异常诊断的导频符号驱动的射频发射系统电退化监测
2012 IEEE 18th International On-Line Testing Symposium (IOLTS) Pub Date : 2012-06-27 DOI: 10.1109/IOLTS.2012.6313860
Sabyasachi Deyati, A. Banerjee, A. Chatterjee
{"title":"Pilot symbol driven monitoring of electrical degradation in RF transmitter systems using model anomaly diagnosis","authors":"Sabyasachi Deyati, A. Banerjee, A. Chatterjee","doi":"10.1109/IOLTS.2012.6313860","DOIUrl":"https://doi.org/10.1109/IOLTS.2012.6313860","url":null,"abstract":"Modern RF circuits suffer from increased electrical degradation induced by electrical stress and thermal effects due to the high speeds of operation and the effects of technology scaling. Detection of such degradation is important, particularly in wireless basestations which must operate round-the-clock with high dependability. In this paper, a new approach for detecting degradation in RF transmitter systems using pilot symbols is proposed and is superior to prior algorithms because degradation can be monitored on a frame-to-frame basis independent of the data being transmitted. The response of the RF transmitter to known pilot symbols is captured at the output of the RF power amplifier using an envelope detector and is fitted to a third order transmitter model using a model-parameter solving algorithm. It is shown that the computed model parameters deviate away from their nominal values, exhibiting model anomalies once nonidealities due to electrical degradation start affecting transmitter behavior. The amount of the degradation is proportional to the magnitude of this deviation as measured by a distance metric and is easily computed using simple algorithms running on the baseband processor. Preliminary results indicate the feasibility and low cost of the proposed approach.","PeriodicalId":246222,"journal":{"name":"2012 IEEE 18th International On-Line Testing Symposium (IOLTS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129218479","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Neutron radiation test of graphic processing units 图形处理装置的中子辐射试验
2012 IEEE 18th International On-Line Testing Symposium (IOLTS) Pub Date : 2012-06-27 DOI: 10.1109/IOLTS.2012.6313841
P. Rech, C. Aguiar, R. Ferreira, C. Frost, L. Carro
{"title":"Neutron radiation test of graphic processing units","authors":"P. Rech, C. Aguiar, R. Ferreira, C. Frost, L. Carro","doi":"10.1109/IOLTS.2012.6313841","DOIUrl":"https://doi.org/10.1109/IOLTS.2012.6313841","url":null,"abstract":"This paper reports and analyzes the results of neutrons radiation testing campaigns on a modern commercial-off-the-shelf Graphic Processing Unit (GPU). A set of guidelines for accelerated radiation experiments on CPUs is presented, emphasizing the shrewdness necessary to ease the test and gain meaningful data. Radiation test results are presented and discussed, highlighting the neutrons sensitivities of the different GPU memory and logic resources in terms of Failure In Time (FIT) due to neutrons at sea level.","PeriodicalId":246222,"journal":{"name":"2012 IEEE 18th International On-Line Testing Symposium (IOLTS)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127749965","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 28
Do more camera pixels result in a better picture? 相机像素越多,照片就越好吗?
2012 IEEE 18th International On-Line Testing Symposium (IOLTS) Pub Date : 2012-06-27 DOI: 10.1109/IOLTS.2012.6313844
G. Chapman, I. Koren, Z. Koren
{"title":"Do more camera pixels result in a better picture?","authors":"G. Chapman, I. Koren, Z. Koren","doi":"10.1109/IOLTS.2012.6313844","DOIUrl":"https://doi.org/10.1109/IOLTS.2012.6313844","url":null,"abstract":"A digital camera sensor will incur pixel defects both in fabrication and during its lifetime. While manufacturing defects are corrected in the factory, in-field defects are prohibitively expensive to fix, and can eventually affect the picture quality. During the last 10 years, we have conducted a study of defect development in digital imagers, in which we had access to about 40 cameras and a database of past photos taken by them. The data we collected allows us to quantify characteristics of defect growth. Our investigations have shown that pixel defects are permanent, and their number grows with time. We found that the main type of defect is hot pixels, which are pixels that appear as a bright spot in the image even without any illumination. We also observed that the defects are distributed randomly over the sensor area and are not clustered. By studying past pictures of each given camera we found that the defect growth rate is constant over time. These spatial and temporal characteristics led us to the conclusion that defects are not likely related to material degradation or imperfect fabrication, but are caused by environmental stress such as cosmic rays radiation. Measuring the effect on the defect rate of sensor parameters such as sensor area, number of pixels, pixel size, and sensor technology (CCD - Charge Coupled Device vs. APS - Active Pixel Sensor) yielded a power law, implying that increasing the number of pixels by shrinking the pixel size will result in a higher defect rate and is, therefore, not recommended.","PeriodicalId":246222,"journal":{"name":"2012 IEEE 18th International On-Line Testing Symposium (IOLTS)","volume":"599 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116462756","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
On line monitoring of RF power amplifiers with embedded temperature sensors 嵌入式温度传感器射频功率放大器的在线监测
2012 IEEE 18th International On-Line Testing Symposium (IOLTS) Pub Date : 2012-06-27 DOI: 10.1109/IOLTS.2012.6313850
J. Altet, D. Mateo, D. Gómez
{"title":"On line monitoring of RF power amplifiers with embedded temperature sensors","authors":"J. Altet, D. Mateo, D. Gómez","doi":"10.1109/IOLTS.2012.6313850","DOIUrl":"https://doi.org/10.1109/IOLTS.2012.6313850","url":null,"abstract":"In the present paper we analyze that DC temperature measurements of the silicon surface can be used to monitor the high frequency status and performances of class A RF Power Amplifiers. As a proof of concept, we present experimental results obtained with a 65 nm CMOS IC that contains a 2 GHz linear class A Power Amplifier and a very simple differential temperature sensor. Results show that the PA output power can be tracked from DC temperature measurements.","PeriodicalId":246222,"journal":{"name":"2012 IEEE 18th International On-Line Testing Symposium (IOLTS)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129492691","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Fault-based reliable design-on-upper-bound of electronic systems for terrestrial radiation including muons, electrons, protons and low energy neutrons 基于故障的地面辐射电子系统上界可靠设计,包括介子、电子、质子和低能中子
2012 IEEE 18th International On-Line Testing Symposium (IOLTS) Pub Date : 2012-06-27 DOI: 10.1109/IOLTS.2012.6313840
E. Ibe, Tadanobu Toba, K. Shimbo, H. Taniguchi
{"title":"Fault-based reliable design-on-upper-bound of electronic systems for terrestrial radiation including muons, electrons, protons and low energy neutrons","authors":"E. Ibe, Tadanobu Toba, K. Shimbo, H. Taniguchi","doi":"10.1109/IOLTS.2012.6313840","DOIUrl":"https://doi.org/10.1109/IOLTS.2012.6313840","url":null,"abstract":"In-depth study on environmental radiation spectra of neutrons, protons, muons, electrons, gamma rays are carried out. Soft-error rates in 130nm SRAMs are estimated based on the survey results with the following conclusions: (1) Charge deposition by muons is relatively high when the muons penetrate p-wells in SRAMs, suggesting current devices have been already affected if the critical charge is below 1fC. (2) Electrons and gamma rays may have certain impacts when the critical charge reduces as low as 0.05fC, suggesting CMOS devices will be safe for at least near future against soft error by electrons and gamma rays. (3) Soft error rates due to both muons and electrons drastically increase as critical charge reduced below certain threshold values.","PeriodicalId":246222,"journal":{"name":"2012 IEEE 18th International On-Line Testing Symposium (IOLTS)","volume":"55 44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130312808","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
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