M. Vilchis, R. Venkatraman, Enrico Costenaro, D. Alexandrescu
{"title":"协同设计流导向SER分析的实际应用","authors":"M. Vilchis, R. Venkatraman, Enrico Costenaro, D. Alexandrescu","doi":"10.1109/IOLTS.2012.6313839","DOIUrl":null,"url":null,"abstract":"We present a methodology that investigates SEEs in complex SOCs. The analysis integrates tightly with the design flow and provides static and dynamic de-rating algorithms. This approach is in good agreement with alpha testing results obtained from a 40nm CMOS testchip with sixty-four independently controlled/selectable Advanced Encryption Standard (AES) based processing element (PE) blocks.","PeriodicalId":246222,"journal":{"name":"2012 IEEE 18th International On-Line Testing Symposium (IOLTS)","volume":"147 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"A real-case application of a synergetic design-flow-oriented SER analysis\",\"authors\":\"M. Vilchis, R. Venkatraman, Enrico Costenaro, D. Alexandrescu\",\"doi\":\"10.1109/IOLTS.2012.6313839\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We present a methodology that investigates SEEs in complex SOCs. The analysis integrates tightly with the design flow and provides static and dynamic de-rating algorithms. This approach is in good agreement with alpha testing results obtained from a 40nm CMOS testchip with sixty-four independently controlled/selectable Advanced Encryption Standard (AES) based processing element (PE) blocks.\",\"PeriodicalId\":246222,\"journal\":{\"name\":\"2012 IEEE 18th International On-Line Testing Symposium (IOLTS)\",\"volume\":\"147 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2012-06-27\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2012 IEEE 18th International On-Line Testing Symposium (IOLTS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IOLTS.2012.6313839\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 IEEE 18th International On-Line Testing Symposium (IOLTS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IOLTS.2012.6313839","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A real-case application of a synergetic design-flow-oriented SER analysis
We present a methodology that investigates SEEs in complex SOCs. The analysis integrates tightly with the design flow and provides static and dynamic de-rating algorithms. This approach is in good agreement with alpha testing results obtained from a 40nm CMOS testchip with sixty-four independently controlled/selectable Advanced Encryption Standard (AES) based processing element (PE) blocks.