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2016 IEEE 46th International Symposium on Multiple-Valued Logic (ISMVL)最新文献

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Formal Design of Pipelined GF Arithmetic Circuits and Its Application to Cryptographic Processors 流水线GF算术电路的形式化设计及其在密码处理器中的应用
2016 IEEE 46th International Symposium on Multiple-Valued Logic (ISMVL) Pub Date : 2016-05-18 DOI: 10.1109/ISMVL.2016.25
Rei Ueno, Yukihiro Sugawara, N. Homma, T. Aoki
{"title":"Formal Design of Pipelined GF Arithmetic Circuits and Its Application to Cryptographic Processors","authors":"Rei Ueno, Yukihiro Sugawara, N. Homma, T. Aoki","doi":"10.1109/ISMVL.2016.25","DOIUrl":"https://doi.org/10.1109/ISMVL.2016.25","url":null,"abstract":"This study presents a formal approach to designing pipelined arithmetic circuits over Galois fields (GFs). The proposed method extends a graph-based circuit description known as a Galois-field arithmetic circuit graph (GF-ACG) to Linear-time Temporal Logic (LTL) in order to represent the timing property of pipelined circuits. We first present the extension of GF-ACG and its formal verification using computer algebra. We then demonstrate the efficiency of the proposed method through an experimental design of a lightweight cryptographic processor. In particular, we design a tamper-resistant datapath with threshold Implementation (TI) based on pipelining and multi-party computation. The proposed method can verify the processor within 1 h, whereas conventional methods would fail.","PeriodicalId":246194,"journal":{"name":"2016 IEEE 46th International Symposium on Multiple-Valued Logic (ISMVL)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2016-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114374097","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
An FFT Circuit Using Nested RNS in a Digital Spectrometer for a Radio Telescope 射电望远镜数字光谱仪中嵌套RNS的FFT电路
2016 IEEE 46th International Symposium on Multiple-Valued Logic (ISMVL) Pub Date : 2016-05-18 DOI: 10.1109/ISMVL.2016.35
Hiroki Nakahara, Tsutomu Sasao, H. Nakanishi, K. Iwai, T. Nagao, Naoya Ogawa
{"title":"An FFT Circuit Using Nested RNS in a Digital Spectrometer for a Radio Telescope","authors":"Hiroki Nakahara, Tsutomu Sasao, H. Nakanishi, K. Iwai, T. Nagao, Naoya Ogawa","doi":"10.1109/ISMVL.2016.35","DOIUrl":"https://doi.org/10.1109/ISMVL.2016.35","url":null,"abstract":"A radio telescope analyzes radio frequency (RF) signal received from celestial objects. It consists of an antenna, a receiver, and a spectrometer. The spectrometer converts the time domain signal into the frequency domain signal by an FFT operation. This paper proposes an FFT circuit based on nested residue number system (NRNS). Since the FFT operation is the most computationally intensive part, parallel implementation is necessary to realize a high-speed FFT. We used an FPGA to implement the circuit. The FPGA consists of look-up tables (LUTs) and block RAMs (BRAMs). For direct parallel FFT realization using an existing FPGA library, the number of LUTs for the complex multipliers is the bottleneck. To reduce the number of LUTs in an FPGA, we increase the dynamic range stage by stage. In this case, NRNS2NRNS converters that convert smaller dynamic range to larger dynamic range are necessary. We implemented the proposed NRNS FFT on the Xilinx Corp. Virtex 7 FPGA. Compared with a conventional binary FFT, although the number of block RAMs (BRAMs) was increased by 20.0-156.5%, in the RNS FFT, the number of LUTs was decreased by 42.4-47.8%and the maximum clock frequency was increased by 9.3-41.7%.With this technique, we successfully implemented an FFT that satisfied the required size and speed specifications on an available FPGA, since the excessive number of LUTs was the bottleneck of the binary FFT.","PeriodicalId":246194,"journal":{"name":"2016 IEEE 46th International Symposium on Multiple-Valued Logic (ISMVL)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2016-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124685614","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Bit-Vector Approach to Satisfiability Testing in Finitely-Valued Logics 有限值逻辑可满足性检验的位向量方法
2016 IEEE 46th International Symposium on Multiple-Valued Logic (ISMVL) Pub Date : 2016-05-18 DOI: 10.1109/ISMVL.2016.47
Joan Ramon Soler, F. Manyà
{"title":"A Bit-Vector Approach to Satisfiability Testing in Finitely-Valued Logics","authors":"Joan Ramon Soler, F. Manyà","doi":"10.1109/ISMVL.2016.47","DOIUrl":"https://doi.org/10.1109/ISMVL.2016.47","url":null,"abstract":"We define a new bit-vector approach for reducing the satisfiability problem of any finitely-valued logic to SAT. Our approach consists of first encoding both the finitely-valued logic and the formula under consideration as an SMT program under the logic of quantifier-free uninterpreted functions and bit vectors (QF_UFBV), and then automatically derive a SAT instance using flattening techniques and efficient CNF conversion algorithms. Moreover, we report on an experimental investigation that shows that the proposed approach is competitive.","PeriodicalId":246194,"journal":{"name":"2016 IEEE 46th International Symposium on Multiple-Valued Logic (ISMVL)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2016-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126876454","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Logic Synthesis for Quantum State Generation 量子态生成的逻辑综合
2016 IEEE 46th International Symposium on Multiple-Valued Logic (ISMVL) Pub Date : 2016-05-18 DOI: 10.1109/ISMVL.2016.30
Philipp Niemann, R. Datta, R. Wille
{"title":"Logic Synthesis for Quantum State Generation","authors":"Philipp Niemann, R. Datta, R. Wille","doi":"10.1109/ISMVL.2016.30","DOIUrl":"https://doi.org/10.1109/ISMVL.2016.30","url":null,"abstract":"Quantum computation established itself as a promising emerging technology and, hence, attracted considerable attention in the domain of computer-aided-design (CAD). However, quantum mechanical phenomena such as superposition, phase shifts, or entanglement lead to a logic model which poses serious challenges to the development of a proper design flow for quantum circuits. Consequently, researchers addressed synthesis of quantum circuits not as a single design step, but considered sub-tasks such as synthesis of Boolean components or synthesis of restricted subsets of quantum functionality. Generating a particularly desired quantum state is another of these sub-tasks. However, logic synthesis of quantum circuits accomplishing that has hardly been considered yet. In this work, we propose a generic method which automatically synthesizes a quantum circuit generating any desired quantum state from an initially given basis state. The proposed method allows for both, a theoretical determination of upper bounds as well as an experimental evaluation of the number of quantum gates needed for this important design step.","PeriodicalId":246194,"journal":{"name":"2016 IEEE 46th International Symposium on Multiple-Valued Logic (ISMVL)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2016-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114023547","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 24
An Algebraic Approach to Reducing the Number of Variables of Incompletely Defined Discrete Functions 不完全定义离散函数中变量数减少的代数方法
2016 IEEE 46th International Symposium on Multiple-Valued Logic (ISMVL) Pub Date : 2016-05-18 DOI: 10.1109/ISMVL.2016.18
J. Astola, P. Astola, R. Stankovic, I. Tabus
{"title":"An Algebraic Approach to Reducing the Number of Variables of Incompletely Defined Discrete Functions","authors":"J. Astola, P. Astola, R. Stankovic, I. Tabus","doi":"10.1109/ISMVL.2016.18","DOIUrl":"https://doi.org/10.1109/ISMVL.2016.18","url":null,"abstract":"In this paper, we consider incompletely defined discrete functions, i.e., Boolean and multiple-valued functions, f:S→{0,1,...,q-1} where S ⊆ {0,1,...,q-1}n i.e.,the function value is specified only on a certain subset S of the domain of the corresponding completely defined function. We assume the function to be sparse i.e. |S| is 'small' relative to the cardinality of the domain. We show that by embedding the domain {0,1,...,q-1}n, where n is the number of variables and q is a prime power, in a suitable ring structure, the multiplicative structure of the ring can be used to construct a linear function {0,1,...,q-1}n {0,1,...,q-1}m that is injective on S provided that m > 2logq |S| + logq(n - 1). In this way we find a linear transform that reduces the number of variables from n to m, and can be used e.g. in implementation of an incompletely defined discrete function by using linear decomposition.","PeriodicalId":246194,"journal":{"name":"2016 IEEE 46th International Symposium on Multiple-Valued Logic (ISMVL)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2016-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114726523","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Dependency Analysis of BMI in Health Checkup Blood Data BMI对健康体检血液数据的依赖性分析
2016 IEEE 46th International Symposium on Multiple-Valued Logic (ISMVL) Pub Date : 2016-05-18 DOI: 10.1109/ISMVL.2016.31
Mizuki Higuchi, Ken-ichi Sorachi, Y. Hata
{"title":"Dependency Analysis of BMI in Health Checkup Blood Data","authors":"Mizuki Higuchi, Ken-ichi Sorachi, Y. Hata","doi":"10.1109/ISMVL.2016.31","DOIUrl":"https://doi.org/10.1109/ISMVL.2016.31","url":null,"abstract":"This paper analyzes the relationship between the change of Body Mass Index (BMI) in one year and the medical examination value of a specific health checkup. To determine this, we divided subjects into 13 groups by BMI changes. We calculated the variation in one year in each group and classify this variation into gender, age, and obesity levels. Our result shows men tend to be more susceptible from variation of BMI. For low and high BMI, some inspection items have the different relationships to change as other items. Some relationships are different depending on gender, age, and obesity levels.","PeriodicalId":246194,"journal":{"name":"2016 IEEE 46th International Symposium on Multiple-Valued Logic (ISMVL)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2016-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130200300","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Realization of Associative Image Search: Development of Image Retrieval Platform for Enhancing Serendipity 关联图像检索的实现:增强偶然性的图像检索平台的开发
2016 IEEE 46th International Symposium on Multiple-Valued Logic (ISMVL) Pub Date : 2016-05-18 DOI: 10.1109/ISMVL.2016.43
M. Haseyama
{"title":"Realization of Associative Image Search: Development of Image Retrieval Platform for Enhancing Serendipity","authors":"M. Haseyama","doi":"10.1109/ISMVL.2016.43","DOIUrl":"https://doi.org/10.1109/ISMVL.2016.43","url":null,"abstract":"This paper presents \"Associative Image Search\", a new image retrieval scheme and its specific engineering application, which enable value creation from big data. The main aim of the associative image search is the realization of information retrieval that enhances the potential for serendipities by providing users with new awareness. Thus, this paper presents the details of research for realizing associative image retrieval. Furthermore, as an example of its applications, a Biomimetics image retrieval platform is also introduced in this paper. By associatively and collaboratively using data accumulated in the fields of biology and material science, the Biomimetics image retrieval platform enables acceleration of their knowledge sharing in different research fields. From retrieval results actually obtained from this platform, there is discussion of the potential of serendipities such as new knowledge emergence.","PeriodicalId":246194,"journal":{"name":"2016 IEEE 46th International Symposium on Multiple-Valued Logic (ISMVL)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2016-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132590881","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A Low-Voltage and Low-Power CMOS Temperature Sensor Circuit with Digital Output for Wireless Healthcare Monitoring System 一种用于无线医疗监测系统的低电压低功耗CMOS数字输出温度传感器电路
2016 IEEE 46th International Symposium on Multiple-Valued Logic (ISMVL) Pub Date : 2016-05-18 DOI: 10.1109/ISMVL.2016.53
Agung Setia Budi, Ryota Sakamoto, H. Tamura, K. Tanno
{"title":"A Low-Voltage and Low-Power CMOS Temperature Sensor Circuit with Digital Output for Wireless Healthcare Monitoring System","authors":"Agung Setia Budi, Ryota Sakamoto, H. Tamura, K. Tanno","doi":"10.1109/ISMVL.2016.53","DOIUrl":"https://doi.org/10.1109/ISMVL.2016.53","url":null,"abstract":"This paper describes a low-voltage and low-power temperature sensor circuit with digital interface for wireless healthcare monitoring system. The proposed circuit consists of temperature sensor core circuit and digital interface circuit. Both circuits are able to be operated at 1.0 V. The proposed temperature sensor circuit is operated in weak inversion region of MOSFETs. The proposed digital interface circuit converts current into time using Current-to-Time Converter (ITC). The proposed circuit is simulated using HSPICE with 1P, 5M, 3-well, 0.18-μm CMOS process (BSIM3v3.2, LEVEL53). From the simulation, it is obtained that temperature range is 33 °C to 45 °C, resolution of proposed circuit is 0.059 °C with +0.076/-0.075 °C inaccuracy and the total power consumption is 23.2 μW.","PeriodicalId":246194,"journal":{"name":"2016 IEEE 46th International Symposium on Multiple-Valued Logic (ISMVL)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2016-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123681668","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Gray-Scale Morphology Based Image Segmentation and Character Extraction Using SVM 基于支持向量机的灰度形态学图像分割与特征提取
2016 IEEE 46th International Symposium on Multiple-Valued Logic (ISMVL) Pub Date : 2016-05-18 DOI: 10.1109/ISMVL.2016.38
Jianjun Chen, N. Takagi
{"title":"Gray-Scale Morphology Based Image Segmentation and Character Extraction Using SVM","authors":"Jianjun Chen, N. Takagi","doi":"10.1109/ISMVL.2016.38","DOIUrl":"https://doi.org/10.1109/ISMVL.2016.38","url":null,"abstract":"Signs and notices are widely used for finding public places and other locations. However, information on signs or notices is inaccessible to many visually impaired people. Therefore, automatically reading text from natural scene images becomes an important application to assist the visually impaired. However, finding text in scene images is a great challenge because it cannot be assumed that the acquired image contains only characters. Natural scene images usually contain diverse text in different size, fonts, orientations and colors, and complex backgrounds such as windows, bricks, and character-like texture. Therefore, this paper proposes a new method to support the scene text reading. This method mainly includes tow parts: (1) image segmentation and, (2) character extraction. The algorithm is implemented and evaluated using a set of natural scene images. Accuracy of the proposed method are calculated and analyzed to determine the success and limitations. Recommendations for improvements are given based on the results.","PeriodicalId":246194,"journal":{"name":"2016 IEEE 46th International Symposium on Multiple-Valued Logic (ISMVL)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2016-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128235420","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Tolerance Distances on Minimal Coverings 最小覆盖层的公差距离
2016 IEEE 46th International Symposium on Multiple-Valued Logic (ISMVL) Pub Date : 2016-05-18 DOI: 10.1109/ISMVL.2016.13
Catalin Zara, D. Simovici
{"title":"Tolerance Distances on Minimal Coverings","authors":"Catalin Zara, D. Simovici","doi":"10.1109/ISMVL.2016.13","DOIUrl":"https://doi.org/10.1109/ISMVL.2016.13","url":null,"abstract":"We define distances on the space of minimal coverings of a finite set that generalize entropy distances on partitions, and establish connections between these spaces. The metric space of minimal coverings has multiple applications in machine learning and data mining, in areas such as multi-label classifications and determination of frequent item sets.","PeriodicalId":246194,"journal":{"name":"2016 IEEE 46th International Symposium on Multiple-Valued Logic (ISMVL)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2016-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129122516","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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