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2016 IEEE 46th International Symposium on Multiple-Valued Logic (ISMVL)最新文献

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An Improved Factorization Approach to Reversible Circuit Synthesis Based on EXORs of Products of EXORs 一种基于EXORs产品的改进型可逆电路合成分解方法
2016 IEEE 46th International Symposium on Multiple-Valued Logic (ISMVL) Pub Date : 2016-05-18 DOI: 10.1109/ISMVL.2016.56
Linh Tran, Addison Gronquist, M. Perkowski, IV JohnS.Caughman
{"title":"An Improved Factorization Approach to Reversible Circuit Synthesis Based on EXORs of Products of EXORs","authors":"Linh Tran, Addison Gronquist, M. Perkowski, IV JohnS.Caughman","doi":"10.1109/ISMVL.2016.56","DOIUrl":"https://doi.org/10.1109/ISMVL.2016.56","url":null,"abstract":"This paper introduces new algorithms to synthesize reversible functions using EXOR-sum of Products-of-EXOR-sums (EPOE) structures. The motivation for using these structures is to reduce the number of as well as the sizes of multiple controlled Toffoli gates, and thus the quantum cost. To achieve these reductions the paper generalizes from existing 2-level AND-EXOR structures (ESOP) commonly used in reversible logic to a mixture of 3-level EXOR-AND-EXOR structures and ESOPs. Our approach can be applied to reversible and permutative quantum circuits to synthesize single output functions on to an output line, with no additional ancilla bits. A comparison of the ESOP minimizer EXORCISM-4 and two variants of the EPOE minimizer, called EPOEM-1s and EPOEM-2, is presented. The results show that EPOE circuits do in fact achieve the above-stated cost reductions, in particular when expressed in terms of Maslov's quantum cost, the metric commonly used in quantum circuit synthesis.","PeriodicalId":246194,"journal":{"name":"2016 IEEE 46th International Symposium on Multiple-Valued Logic (ISMVL)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2016-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116259029","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Re-Writing HDL Descriptions for Line-Aware Synthesis of Reversible Circuits 可逆电路线感知合成的HDL描述重写
2016 IEEE 46th International Symposium on Multiple-Valued Logic (ISMVL) Pub Date : 2016-05-18 DOI: 10.1109/ISMVL.2016.36
Zaid Al-Wardi, R. Wille, R. Drechsler
{"title":"Re-Writing HDL Descriptions for Line-Aware Synthesis of Reversible Circuits","authors":"Zaid Al-Wardi, R. Wille, R. Drechsler","doi":"10.1109/ISMVL.2016.36","DOIUrl":"https://doi.org/10.1109/ISMVL.2016.36","url":null,"abstract":"Reversible computing is a promising research field due to its applications in several emerging technologies. Accordingly, several approaches for the design of reversible circuits have been introduced - including solutions realizing functionality provided in terms of hardware description languages. Their main drawback is, however, that they require a substantial amount of additional circuit lines. While some solutions addressing this problem have been proposed in the past, the contribution of the respectively given HDL code to this drawback has hardly been considered yet. In this work, we are considering this problem from this angle: Observations have been conducted which, eventually, led to a set of re-writing rules for a line-aware synthesis of reversible circuits from HDL descriptions. Case studies show the benefits of these rules - in total, substantial reductions in the number of circuit lines have been observed.","PeriodicalId":246194,"journal":{"name":"2016 IEEE 46th International Symposium on Multiple-Valued Logic (ISMVL)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2016-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131626161","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Notes on Majority Boolean Algebra 多数布尔代数注释
2016 IEEE 46th International Symposium on Multiple-Valued Logic (ISMVL) Pub Date : 2016-05-18 DOI: 10.1109/ISMVL.2016.21
A. Chattopadhyay, L. Amarù, Mathias Soeken, P. Gaillardon, G. Micheli
{"title":"Notes on Majority Boolean Algebra","authors":"A. Chattopadhyay, L. Amarù, Mathias Soeken, P. Gaillardon, G. Micheli","doi":"10.1109/ISMVL.2016.21","DOIUrl":"https://doi.org/10.1109/ISMVL.2016.21","url":null,"abstract":"A Majority-Inverter Graph (MIG) is a homogeneous logic network, where each node represents the majority function. Recently, a logic optimization package based on the MIG data structure, with 3-input majority node (M3) has been proposed [2],[30]. It is demonstrated to have efficient area-delay-power results compared to state-of-the-art logic optimization packages. In this paper, the Boolean algebraic transformations based on majority logic, i.e., majority Boolean algebra is studied. In the first part of this paper, we summarize a range of identities for majority Boolean algebra with their corresponding proofs. In the second part, we venture towards heterogeneous logic network and provide reversible logic mapping of majority nodes.","PeriodicalId":246194,"journal":{"name":"2016 IEEE 46th International Symposium on Multiple-Valued Logic (ISMVL)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2016-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133511992","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Design of Ratioless Ternary Inverter Using Graphene Barristor 基于石墨烯电阻器的无比例三元逆变器设计
2016 IEEE 46th International Symposium on Multiple-Valued Logic (ISMVL) Pub Date : 2016-05-18 DOI: 10.1109/ISMVL.2016.51
S. Heo, J. Noh, Yun Ji Kim, So-Young Kim, Abdul Karim Khan, B. Lee
{"title":"Design of Ratioless Ternary Inverter Using Graphene Barristor","authors":"S. Heo, J. Noh, Yun Ji Kim, So-Young Kim, Abdul Karim Khan, B. Lee","doi":"10.1109/ISMVL.2016.51","DOIUrl":"https://doi.org/10.1109/ISMVL.2016.51","url":null,"abstract":"This study proposes a design of a ternary logic inverter using graphene barristor (GB). To design a multiple-valued logic gate, controlling threshold voltages of the unit device should be easy. We determined that the doping concentration of the graphene can easily control the operation voltage of the GB. To realize an ideal ternary logic gate, the concept of a single pole triple throw switch is proposed and designed using the GB. The designed ratioless GB ternary inverter was simulated using SPICE and Mathematica. Voltage transfer characteristics of the proposed ternary inverter showed sharp ternary characteristics and its static power consumption was nearly zero.","PeriodicalId":246194,"journal":{"name":"2016 IEEE 46th International Symposium on Multiple-Valued Logic (ISMVL)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2016-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114628572","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Study Support System of Character Drawing Considering Feeling Evaluation 考虑情感评价的人物绘画学习支持系统
2016 IEEE 46th International Symposium on Multiple-Valued Logic (ISMVL) Pub Date : 2016-05-18 DOI: 10.1109/ISMVL.2016.34
Ryuichi Murakami, N. Muranaka
{"title":"Study Support System of Character Drawing Considering Feeling Evaluation","authors":"Ryuichi Murakami, N. Muranaka","doi":"10.1109/ISMVL.2016.34","DOIUrl":"https://doi.org/10.1109/ISMVL.2016.34","url":null,"abstract":"In the evaluation of the art, the evaluation depends on the examiner. However, in the evaluation like learning, obvious evaluation standard is nothing in this time. Also, the inflexible binary computer cannot do evaluation (multiple-valued logic) like human. Therefore, authors already presented about some drawing support systems of self-education type for beginner. And, that motif is human character. In first research report, scoring evaluation method was \"total of 3 items\". However, this method had no elasticity to be able to evaluate \"position shifting\" or \"similar drawing\". Therefore, in this research, we reconsider the item of the drawing evaluation and we propose the character drawing study support system which can do the feeling evaluation like the human with having strictness and an elasticity.","PeriodicalId":246194,"journal":{"name":"2016 IEEE 46th International Symposium on Multiple-Valued Logic (ISMVL)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2016-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127597415","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Elucidation of Brain Activities by Electroencephalograms and Its Application to Brain Computer Interface 脑电信号对脑活动的阐释及其在脑机接口中的应用
2016 IEEE 46th International Symposium on Multiple-Valued Logic (ISMVL) Pub Date : 2016-05-18 DOI: 10.1109/ISMVL.2016.45
T. Yamanoi
{"title":"Elucidation of Brain Activities by Electroencephalograms and Its Application to Brain Computer Interface","authors":"T. Yamanoi","doi":"10.1109/ISMVL.2016.45","DOIUrl":"https://doi.org/10.1109/ISMVL.2016.45","url":null,"abstract":"In order to develop a brain computer interface (BCI), the present author and his group, yamanoi group, have investigated the brain activity during human recognition of characters and symbols representing directional meaning. Subjects were asked to read them silently. Electroencephalograms (EEGs) were averaged for each stimulus type, and event related potentials (ERPs) were obtained. The equivalent current dipole source localization (ECDL) method has been applied to these ERPs. In both cases, ECDs were localized to areas related to the working memory for spatial perception, i. e. the right upper or the right middle frontal areas. And the opposite directional arrows had opposite dipoles in these areas. Taking into account these facts, the group recorded EEGs from subjects looking and recalling ten types of images of robot movement presented on a CRT. The group investigated a single trial EEGs of the subject precisely after the latency at 400 ms, and determined effective sampling latencies for the discriminant analysis to ten types of images. They sampled EEG data at latencies from 400 ms to 900 ms at 25 ms intervals by the four channels such as Fp2, F4, C4 and F8. Results of the discriminant analysis with jack knife (cross validation) method for ten type objective varieties, the discriminant rates for three subjects were almost 90 %. We could control a micro robot with ten commands only to recall corresponding movement image.","PeriodicalId":246194,"journal":{"name":"2016 IEEE 46th International Symposium on Multiple-Valued Logic (ISMVL)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2016-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132830045","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Study on Realizing Awareness Using 3VL-MLP 利用3VL-MLP实现意识的研究
2016 IEEE 46th International Symposium on Multiple-Valued Logic (ISMVL) Pub Date : 2016-05-18 DOI: 10.1109/ISMVL.2016.9
Qiangfu Zhao
{"title":"A Study on Realizing Awareness Using 3VL-MLP","authors":"Qiangfu Zhao","doi":"10.1109/ISMVL.2016.9","DOIUrl":"https://doi.org/10.1109/ISMVL.2016.9","url":null,"abstract":"Awareness is a way from sensory data to cognition. The main purpose of computational awareness (CA) is to understand the awareness mechanism and realize it in computers. Various awareness are used in our daily lives for making decisions, but most of them are tacit. For the purpose of CA, we need to interpret and understand tacit awareness as far as possible. In our earlier study, we introduced a general graph model of aware systems. In this paper, we focus on the multilayer perceptron (MLP) model, and study the feasibility of interpreting MLPs using 3-valued logic (3VL). The main purpose is to show via experiments on several public data 1) 3VL is more accurate than binary logic for interpreting a trained MLP, 2) the MLP can be more interpretable if we use structural learning with forgetting, and 3) the performance of the discretized MLPs can be improved through retraining. Based on the results obtained here, we will point out some important topics for further study.","PeriodicalId":246194,"journal":{"name":"2016 IEEE 46th International Symposium on Multiple-Valued Logic (ISMVL)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2016-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121460110","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Technology Mapping of Reversible Circuits to Clifford+T Quantum Circuits 可逆电路到Clifford+T量子电路的技术映射
2016 IEEE 46th International Symposium on Multiple-Valued Logic (ISMVL) Pub Date : 2016-05-18 DOI: 10.1109/ISMVL.2016.33
Nabila Abdessaied, M. Amy, Mathias Soeken, R. Drechsler
{"title":"Technology Mapping of Reversible Circuits to Clifford+T Quantum Circuits","authors":"Nabila Abdessaied, M. Amy, Mathias Soeken, R. Drechsler","doi":"10.1109/ISMVL.2016.33","DOIUrl":"https://doi.org/10.1109/ISMVL.2016.33","url":null,"abstract":"The Clifford+T quantum gate library has attracted much interest in the design of quantum circuits, particularly since the contained operations can be implemented in a fault-tolerant manner. Since fault tolerant implementations of the T gate have very high latency, synthesis and optimization are aiming at minimizing the number of T stages, referred to as the T-depth. In this paper, we present an approach to map mixed polarity multiple controlled Toffoli gates into Clifford+T quantum circuits. Our approach is based on the multiple control Toffoli mapping algorithms proposed by Barenco et al., which are given T-depth optimized Clifford+T translations. Experiments show that our approach leads to a significant T-depth reduction of 54% on average.","PeriodicalId":246194,"journal":{"name":"2016 IEEE 46th International Symposium on Multiple-Valued Logic (ISMVL)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2016-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114461805","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 35
Monomial Clones: Local Results and Global Properties 单项式克隆:局部结果和全局属性
2016 IEEE 46th International Symposium on Multiple-Valued Logic (ISMVL) Pub Date : 2016-05-18 DOI: 10.1109/ISMVL.2016.39
Hajime Machida, J. Pantović
{"title":"Monomial Clones: Local Results and Global Properties","authors":"Hajime Machida, J. Pantović","doi":"10.1109/ISMVL.2016.39","DOIUrl":"https://doi.org/10.1109/ISMVL.2016.39","url":null,"abstract":"A monomial clone is a clone which is generated by a monomial. For a prime power k we consider monomial clones on the finite field GF(k). There are two monomial clones on a two-element set and six such clones on a three-element set. Ordered by set inclusion, they form lattices. In the general case, we put emphasis on monomial clones generated by unary and binary monomials. We determine unary minimal monomial clones and binary monomial clones of degree k. Furthermore, we list all unary and binary monomial clones on GF(5) and state several properties that hold on GF(7) and GF(11).","PeriodicalId":246194,"journal":{"name":"2016 IEEE 46th International Symposium on Multiple-Valued Logic (ISMVL)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2016-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126411205","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Gibbs Characterization of Binary and Ternary Bent Functions 二元和三元弯曲函数的吉布斯表征
2016 IEEE 46th International Symposium on Multiple-Valued Logic (ISMVL) Pub Date : 2016-05-18 DOI: 10.1109/ISMVL.2016.23
R. Stankovic, M. Stankovic, J. Astola, C. Moraga
{"title":"Gibbs Characterization of Binary and Ternary Bent Functions","authors":"R. Stankovic, M. Stankovic, J. Astola, C. Moraga","doi":"10.1109/ISMVL.2016.23","DOIUrl":"https://doi.org/10.1109/ISMVL.2016.23","url":null,"abstract":"The paper discusses relationships between bent functions and spectral invariant operations. Considerations are done on examples of binary and ternary bent functions, however, can be generalized to p-ary bent functions for any prime p. We also discuss differences between the binary and ternary cases of a method for characterization of certain classes of bent functions in terms of particular differential operators on finite groups called the Gibbs derivatives.","PeriodicalId":246194,"journal":{"name":"2016 IEEE 46th International Symposium on Multiple-Valued Logic (ISMVL)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2016-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131853530","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
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