Hiroki Nakahara, Tsutomu Sasao, H. Nakanishi, K. Iwai, T. Nagao, Naoya Ogawa
{"title":"射电望远镜数字光谱仪中嵌套RNS的FFT电路","authors":"Hiroki Nakahara, Tsutomu Sasao, H. Nakanishi, K. Iwai, T. Nagao, Naoya Ogawa","doi":"10.1109/ISMVL.2016.35","DOIUrl":null,"url":null,"abstract":"A radio telescope analyzes radio frequency (RF) signal received from celestial objects. It consists of an antenna, a receiver, and a spectrometer. The spectrometer converts the time domain signal into the frequency domain signal by an FFT operation. This paper proposes an FFT circuit based on nested residue number system (NRNS). Since the FFT operation is the most computationally intensive part, parallel implementation is necessary to realize a high-speed FFT. We used an FPGA to implement the circuit. The FPGA consists of look-up tables (LUTs) and block RAMs (BRAMs). For direct parallel FFT realization using an existing FPGA library, the number of LUTs for the complex multipliers is the bottleneck. To reduce the number of LUTs in an FPGA, we increase the dynamic range stage by stage. In this case, NRNS2NRNS converters that convert smaller dynamic range to larger dynamic range are necessary. We implemented the proposed NRNS FFT on the Xilinx Corp. Virtex 7 FPGA. Compared with a conventional binary FFT, although the number of block RAMs (BRAMs) was increased by 20.0-156.5%, in the RNS FFT, the number of LUTs was decreased by 42.4-47.8%and the maximum clock frequency was increased by 9.3-41.7%.With this technique, we successfully implemented an FFT that satisfied the required size and speed specifications on an available FPGA, since the excessive number of LUTs was the bottleneck of the binary FFT.","PeriodicalId":246194,"journal":{"name":"2016 IEEE 46th International Symposium on Multiple-Valued Logic (ISMVL)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2016-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"An FFT Circuit Using Nested RNS in a Digital Spectrometer for a Radio Telescope\",\"authors\":\"Hiroki Nakahara, Tsutomu Sasao, H. Nakanishi, K. Iwai, T. Nagao, Naoya Ogawa\",\"doi\":\"10.1109/ISMVL.2016.35\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A radio telescope analyzes radio frequency (RF) signal received from celestial objects. It consists of an antenna, a receiver, and a spectrometer. The spectrometer converts the time domain signal into the frequency domain signal by an FFT operation. This paper proposes an FFT circuit based on nested residue number system (NRNS). Since the FFT operation is the most computationally intensive part, parallel implementation is necessary to realize a high-speed FFT. We used an FPGA to implement the circuit. The FPGA consists of look-up tables (LUTs) and block RAMs (BRAMs). For direct parallel FFT realization using an existing FPGA library, the number of LUTs for the complex multipliers is the bottleneck. To reduce the number of LUTs in an FPGA, we increase the dynamic range stage by stage. In this case, NRNS2NRNS converters that convert smaller dynamic range to larger dynamic range are necessary. We implemented the proposed NRNS FFT on the Xilinx Corp. Virtex 7 FPGA. Compared with a conventional binary FFT, although the number of block RAMs (BRAMs) was increased by 20.0-156.5%, in the RNS FFT, the number of LUTs was decreased by 42.4-47.8%and the maximum clock frequency was increased by 9.3-41.7%.With this technique, we successfully implemented an FFT that satisfied the required size and speed specifications on an available FPGA, since the excessive number of LUTs was the bottleneck of the binary FFT.\",\"PeriodicalId\":246194,\"journal\":{\"name\":\"2016 IEEE 46th International Symposium on Multiple-Valued Logic (ISMVL)\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-05-18\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 IEEE 46th International Symposium on Multiple-Valued Logic (ISMVL)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISMVL.2016.35\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE 46th International Symposium on Multiple-Valued Logic (ISMVL)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISMVL.2016.35","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
An FFT Circuit Using Nested RNS in a Digital Spectrometer for a Radio Telescope
A radio telescope analyzes radio frequency (RF) signal received from celestial objects. It consists of an antenna, a receiver, and a spectrometer. The spectrometer converts the time domain signal into the frequency domain signal by an FFT operation. This paper proposes an FFT circuit based on nested residue number system (NRNS). Since the FFT operation is the most computationally intensive part, parallel implementation is necessary to realize a high-speed FFT. We used an FPGA to implement the circuit. The FPGA consists of look-up tables (LUTs) and block RAMs (BRAMs). For direct parallel FFT realization using an existing FPGA library, the number of LUTs for the complex multipliers is the bottleneck. To reduce the number of LUTs in an FPGA, we increase the dynamic range stage by stage. In this case, NRNS2NRNS converters that convert smaller dynamic range to larger dynamic range are necessary. We implemented the proposed NRNS FFT on the Xilinx Corp. Virtex 7 FPGA. Compared with a conventional binary FFT, although the number of block RAMs (BRAMs) was increased by 20.0-156.5%, in the RNS FFT, the number of LUTs was decreased by 42.4-47.8%and the maximum clock frequency was increased by 9.3-41.7%.With this technique, we successfully implemented an FFT that satisfied the required size and speed specifications on an available FPGA, since the excessive number of LUTs was the bottleneck of the binary FFT.