A Bit-Vector Approach to Satisfiability Testing in Finitely-Valued Logics

Abstract

We define a new bit-vector approach for reducing the satisfiability problem of any finitely-valued logic to SAT. Our approach consists of first encoding both the finitely-valued logic and the formula under consideration as an SMT program under the logic of quantifier-free uninterpreted functions and bit vectors (QF_UFBV), and then automatically derive a SAT instance using flattening techniques and efficient CNF conversion algorithms. Moreover, we report on an experimental investigation that shows that the proposed approach is competitive.