9th International Symposium on Quality Electronic Design (isqed 2008)最新文献_第2页

A Knowledge-Based Tool for Generating and Verifying Hardware-Ready Embedded Memory Models 基于知识的嵌入式内存模型生成与验证工具

9th International Symposium on Quality Electronic Design (isqed 2008) Pub Date : 2008-03-17 DOI: 10.1109/ISQED.2008.35

P. Cheng

引用次数: 0

Improving the Efficiency of Power Management Techniques by Using Bayesian Classification 利用贝叶斯分类提高电源管理技术的效率

9th International Symposium on Quality Electronic Design (isqed 2008) Pub Date : 2008-03-17 DOI: 10.1109/ISQED.2008.133

Hwisung Jung, Massoud Pedram

引用次数: 19

A Built-in Test and Characterization Method for Circuit Marginality Related Failures 电路边际性相关故障的内置测试和表征方法

9th International Symposium on Quality Electronic Design (isqed 2008) Pub Date : 2008-03-17 DOI: 10.1109/ISQED.2008.51

A. Sanyal, S. Kundu

{"title":"A Built-in Test and Characterization Method for Circuit Marginality Related Failures","authors":"A. Sanyal, S. Kundu","doi":"10.1109/ISQED.2008.51","DOIUrl":"https://doi.org/10.1109/ISQED.2008.51","url":null,"abstract":"With the advent of ultra deep-submicron (UDSM) regime of integrated circuits, the issues with circuit marginality related transient failures are on the rise. An example of such failures is the thermal hotspot-induced ones, which are common when a particular functional unit experiences high switching activity for a considerable duration. In this paper, we propose an on-line hotspot-induced transient failure testing scheme using the built-in self-test (BlST)-based approach which accurately distinguishes such a transient failure from a hard fail and greatly reduces the test cost by dissociating a tester from the test process. We apply the principle of Fmax testing based on frequency shmoo to obtain the maximum safe operating frequency for individual functional units in a chip. We also propose a DFT scheme to characterize the impact of a \"hot\" unit on its neighborhood and also the influence of a \"hot\" neighborhood on an otherwise \"cold\" unit in the reverse way. Thus the proposed architecture extends the capability of the conventional BIST to test a certain class of circuit marginality related transient failures with a very low hardware overhead.","PeriodicalId":243121,"journal":{"name":"9th International Symposium on Quality Electronic Design (isqed 2008)","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124301488","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Variation Aware Spline Center and Range Modeling for Analog Circuit Performance 模拟电路性能变化感知样条中心和范围建模

9th International Symposium on Quality Electronic Design (isqed 2008) Pub Date : 2008-03-17 DOI: 10.1109/ISQED.2008.118

Shubhankar Basu, Balaji Kommineni, R. Vemuri

引用次数: 9

Partitioning for Selective Flip-Flop Redundancy in Sequential Circuits 顺序电路中选择性触发器冗余的分划

9th International Symposium on Quality Electronic Design (isqed 2008) Pub Date : 2008-03-17 DOI: 10.1109/ISQED.2008.143

Uthman Alsaiari, R. Saleh

{"title":"Partitioning for Selective Flip-Flop Redundancy in Sequential Circuits","authors":"Uthman Alsaiari, R. Saleh","doi":"10.1109/ISQED.2008.143","DOIUrl":"https://doi.org/10.1109/ISQED.2008.143","url":null,"abstract":"As the number of transistors on a chip begins to exceed 1 billion and their sensitivity to defects begins to degrade overall yield, it will be mandatory to assign a portion of the transistors for the purposes of built-in- self-test (BIST) and built-in-self-repair (BISR) as part of the supporting circuitry. Here, we focus on the self-test and self-repair of flip-flops (FF's), and their associated interconnect, using spare FF's to replace faulty ones. We describe our method to determine the number of spares based on delay and yield analysis. Using these results, we partition the flip-flops in a sequential design to improve the yield while keeping the delay and area overhead low. Next, we apply this redundancy approach only to non-critical paths in the circuit so that no timing penalty is incurred, and find that it can still provide significant improvement in the overall yield. A number of sequential benchmark circuits from ITC '99 are compared with and without redundant flip-flops, and also with and without partitioning. The total area overhead of our method is 8% on average while improving the yield by 6-29% and incurring no timing penalty.","PeriodicalId":243121,"journal":{"name":"9th International Symposium on Quality Electronic Design (isqed 2008)","volume":"352 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115895745","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Predictive Delay Evaluation on Emerging CMOS Technologies: A Simulation Framework 新兴CMOS技术的预测延迟评估:一个仿真框架

9th International Symposium on Quality Electronic Design (isqed 2008) Pub Date : 2008-03-17 DOI: 10.1109/ISQED.2008.137

M. Sellier, J. Portal, B. Borot, S. Colquhoun, R. Ferrant, F. Boeuf, A. Farcy

引用次数: 6

Clock Skew Analysis via Vector Fitting in Frequency Domain 基于频域矢量拟合的时钟偏差分析

9th International Symposium on Quality Electronic Design (isqed 2008) Pub Date : 2008-03-17 DOI: 10.1109/ISQED.2008.67

Ling Zhang, Wenjian Yu, Haikun Zhu, Wanping Zhang, Chung-Kuan Cheng

{"title":"Clock Skew Analysis via Vector Fitting in Frequency Domain","authors":"Ling Zhang, Wenjian Yu, Haikun Zhu, Wanping Zhang, Chung-Kuan Cheng","doi":"10.1109/ISQED.2008.67","DOIUrl":"https://doi.org/10.1109/ISQED.2008.67","url":null,"abstract":"An efficient frequency-based clock analysis method: CSAV is proposed in this paper. It computes the circuit response by first solving the state equation in frequency domain, and derive the rational approximate with the help of vector fitting [9]. There are two aspects that contribute to the time efficiency of the method. One is CSAV solves the state equation only on selected frequency points, which significantly reduce the amount of time for equation solving. The other is CSAV performs vector fitting and waveform recovery only on user specified nodes, which save the unnecessary computation on the nodes which are not concerned by user. The complexity of our method is O( lceillg fmaxrceilNalpha + lceillg fmaxrceil 2NaNout), where fmax is proportional to the knee frequencyquency of input signal, N is the node number of the circuit, a is a constant around 1.3, Na is the order of approximation and Nout is the number of output nodes. Our experimental results show that compared with Hspice, CSAV achieves speed-up up to 35 times while the error is only 1%. Moreover, computational saving of CSAV grows with circuit size, which makes this method especially promising for large cases.","PeriodicalId":243121,"journal":{"name":"9th International Symposium on Quality Electronic Design (isqed 2008)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131927799","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Process-Variation Statistical Modeling for VLSI Timing Analysis VLSI时序分析的过程变化统计建模

9th International Symposium on Quality Electronic Design (isqed 2008) Pub Date : 2008-03-17 DOI: 10.1109/ISQED.2008.66

Jui-Hsiang Liu, Jun-Kuei Zeng, Ai-Syuan Hong, Lumdo Chen, C. C. Chen

引用次数: 10

A Tunable Clock Buffer for Intra-die PVT Compensation in Single-Edge Clock (SEC) Distribution Networks 一种用于单边缘时钟(SEC)分配网络中模内PVT补偿的可调时钟缓冲器

9th International Symposium on Quality Electronic Design (isqed 2008) Pub Date : 2008-03-17 DOI: 10.1109/ISQED.2008.47

Jeff Mueller, R. Saleh

引用次数: 11

Combinational Logic Circuit Protection Using Customized Error Detecting and Correcting Codes 使用自定义错误检测和纠错码的组合逻辑电路保护

9th International Symposium on Quality Electronic Design (isqed 2008) Pub Date : 2008-03-17 DOI: 10.1109/ISQED.2008.56

Avijit Dutta, A. Jas

{"title":"Combinational Logic Circuit Protection Using Customized Error Detecting and Correcting Codes","authors":"Avijit Dutta, A. Jas","doi":"10.1109/ISQED.2008.56","DOIUrl":"https://doi.org/10.1109/ISQED.2008.56","url":null,"abstract":"Detecting and correcting errors in logic circuits is much more difficult than in memories. While concurrent error detection and correction mechanisms can be efficiently incorporated in memories due to their regular structure, logic circuits present a much greater challenge because of their irregular structure. One approach to handle the problems arising due to soft errors is to detect the errors using a concurrent error detection (CED) circuitry that monitors the circuit output for the occurrence of an error. Once the error is detected the system can recover and hence prevent a failure. While operating in an environment with high soft error rate and for systems with a stringent reliability and availability requirement, error detection alone may not be sufficient. While triple modular redundancy (TMR) can mask all single faults, the overhead can be unacceptably high for the targeted applications. This paper presents a low-overhead non-intrusive technique to detect and correct the most likely soft errors using customized ad-hoc error detecting and correcting (EDAC) linear block codes. Employing the proposed EDAC scheme can dramatically reduce the failure rate and increase the mean time to failure (MTTF) for logic circuits with limited overhead. For certain types of applications e.g., network servers, query servers, etc., with high availability and low cost requirements, the proposed approach could be very useful. The linearity property of the codes allows for efficient synthesis of the parity prediction logic. The experimental results demonstrate the effectiveness of the proposed scheme.","PeriodicalId":243121,"journal":{"name":"9th International Symposium on Quality Electronic Design (isqed 2008)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130873428","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6