9th International Symposium on Quality Electronic Design (isqed 2008)最新文献_第3页

Noise-Aware On-Chip Power Grid Considerations Using a Statistical Approach 利用统计方法考虑片上电网的噪声

9th International Symposium on Quality Electronic Design (isqed 2008) Pub Date : 2008-03-17 DOI: 10.1109/ISQED.2008.148

D. Andersson, L. Svensson, P. Larsson-Edefors

引用次数: 6

Crosstalk Noise Variation Assessment and Analysis for the Worst Process Corner 最坏过程角的串扰噪声变化评价与分析

9th International Symposium on Quality Electronic Design (isqed 2008) Pub Date : 2008-03-17 DOI: 10.1109/ISQED.2008.22

Jae-Seok Yang, A. Neureuther

引用次数: 3

Amplifying Embedded System Efficiency via Automatic Instruction Fusion on a Post-Manufacturing Reconfigurable Architecture Platform 基于制造后可重构架构平台的自动指令融合提高嵌入式系统效率

9th International Symposium on Quality Electronic Design (isqed 2008) Pub Date : 2008-03-17 DOI: 10.1109/ISQED.2008.85

A. Cheng

{"title":"Amplifying Embedded System Efficiency via Automatic Instruction Fusion on a Post-Manufacturing Reconfigurable Architecture Platform","authors":"A. Cheng","doi":"10.1109/ISQED.2008.85","DOIUrl":"https://doi.org/10.1109/ISQED.2008.85","url":null,"abstract":"Portable embedded SoC processor architects are constantly challenged by exponentially increasing demand for newer functionality, faster real-time communication, stronger security, and higher reliability; while the constraint on energy, feature size, NRE cost, and time-to-market (TTM) grows tighter than ever. Existing approaches attempting to achieve these mutual conflicting design goals rely heavily on adopting special-purpose accelerators (SPA) to take charge of the heavy lifting in the aimed embedded SoC designs. These SPAs, synthesized from either ASIC or FPGA, are usually augmented to the base processor as co-processors to execute the performance-critical regions of applications. ASIC-based SPAs achieve performance-energy efficiency at the expense of sacrificing post-manufacturing programmability while incurring large NRE and TTM; FPGA-based SPAs retain programmability at the expense of significant energy and area increase. Furthermore, augmenting these SPAs as co-processors adds considerable communication and synchronization overhead severely compromising their initially promised benefits. This paper proposes an innovative design paradigm that moves away from the common scheme of adding co-processing ASIC/FPGA SPAs to an integrated and reconfigurable design. Specifically, we propose a new class of embedded processor by replacing the processor's conventional ALU with a more powerful and flexible versatile processing unit (VPU). VPU enables multiple interdependent instructions to be fused and processed together as a single atomic VPU instruction by exploring dataflow dependencies of the application code. The instruction fusion is automatically performed by a VPU-aware compiler. The optimized VPU code reduces code size and amplifies the effective processor bandwidth and capacity by eliminating transient computation and register spill code. Experimental results show up to 400% and average 150% speedup for MediaBench with negligible area increase.","PeriodicalId":243121,"journal":{"name":"9th International Symposium on Quality Electronic Design (isqed 2008)","volume":"179 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116173475","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Statistic Analysis of Power/Ground Networks Using Single-Node SOR Method 基于单节点SOR法的电力/地面网络统计分析

9th International Symposium on Quality Electronic Design (isqed 2008) Pub Date : 2008-03-17 DOI: 10.1109/ISQED.2008.62

Zuying Luo, S. Tan

引用次数: 5

Analytical Noise-Rejection Model Based on Short Channel MOSFET 基于短通道MOSFET的解析噪声抑制模型

9th International Symposium on Quality Electronic Design (isqed 2008) Pub Date : 2008-03-17 DOI: 10.1109/ISQED.2008.166

V. Jain, P. Zarkesh-Ha

引用次数: 1

Adaptive Stochastic Collocation Method (ASCM) for Parameterized Statistical Timing Analysis with Quadratic Delay Model 二次延迟模型参数化统计时序分析的自适应随机配置方法

9th International Symposium on Quality Electronic Design (isqed 2008) Pub Date : 2008-03-17 DOI: 10.1093/ietfec/e91-a.12.3465

Yi Wang, Xuan Zeng, J. Tao, Hengliang Zhu, Xu Luo, Changhao Yan, W. Cai

{"title":"Adaptive Stochastic Collocation Method (ASCM) for Parameterized Statistical Timing Analysis with Quadratic Delay Model","authors":"Yi Wang, Xuan Zeng, J. Tao, Hengliang Zhu, Xu Luo, Changhao Yan, W. Cai","doi":"10.1093/ietfec/e91-a.12.3465","DOIUrl":"https://doi.org/10.1093/ietfec/e91-a.12.3465","url":null,"abstract":"In this paper, we propose an adaptive stochastic collocation method for block-based statistical static timing analysis (SSTA). A novel adaptive method is proposed to perform SSTA with delays of gates and interconnects modeled by quadratic polynomials based on homogeneous chaos expansion. In order to approximate the key atomic operator MAX in the full random space during timing analysis, the proposed method adaptively chooses the optimal algorithm from a set of stochastic collocation methods by considering different input conditions. Compared with the existing stochastic collocation methods, including the one using dimension reduction technique and the one using sparse grid technique, the proposed method has 10times improvements in the accuracy while using the same order of computation time. The proposed algorithm also show great improvement in accuracy compared with a moment matching method. Compared with the 10,000 Monte Carlo simulations on ISCAS85 benchmark circuits, the results of the proposed method show less than 1% error in the mean and variance, and nearly 100times speeds up.","PeriodicalId":243121,"journal":{"name":"9th International Symposium on Quality Electronic Design (isqed 2008)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132417429","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

Modeling of NBTI-Induced PMOS Degradation under Arbitrary Dynamic Temperature Variation 任意动态温度变化下nbti诱导PMOS降解的建模

9th International Symposium on Quality Electronic Design (isqed 2008) Pub Date : 2008-03-17 DOI: 10.1109/ISQED.2008.151

Bin Zhang, M. Orshansky

{"title":"Modeling of NBTI-Induced PMOS Degradation under Arbitrary Dynamic Temperature Variation","authors":"Bin Zhang, M. Orshansky","doi":"10.1109/ISQED.2008.151","DOIUrl":"https://doi.org/10.1109/ISQED.2008.151","url":null,"abstract":"Negative bias temperature instability (NBTI) is one of the primary limiters of reliability lifetime in nano-scale integrated circuits. NBTI manifests itself in a gradual increase in the magnitude of PMOS threshold voltage, resulting in the degradation of circuit performance over time. NBTI is highly sensitive to operating temperature, making the amount of degradation strongly dependent on the thermal history of the chip. In order to accurately predict the amount of threshold voltage increase, the precise temperature profile must be utilized. The existing models are based on the simplified analysis which assumes that the temperature takes up to two possible fixed values over time. These models are inaccurate when predicting the impact of continuously-changing temperature that spans a large range. Our experiments show that proposed model accounting for temperature variation provides a significantly tighter bound for the simulation than that from the model that ignores the temperature variation and assumes a constant (worst-case) temperature. In our experiment, the amount of degradation predicted by the proposed dynamic temperature model is on average 46% less conservative compared to the model based on the worst-case temperature.","PeriodicalId":243121,"journal":{"name":"9th International Symposium on Quality Electronic Design (isqed 2008)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133013114","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 46

Reliability-Aware Optimization for DVS-Enabled Real-Time Embedded Systems 支持dvs的实时嵌入式系统的可靠性感知优化

9th International Symposium on Quality Electronic Design (isqed 2008) Pub Date : 2008-03-17 DOI: 10.1109/ISQED.2008.161

F. Dabiri, Navid Amini, Mahsan Rofouei, M. Sarrafzadeh

{"title":"Reliability-Aware Optimization for DVS-Enabled Real-Time Embedded Systems","authors":"F. Dabiri, Navid Amini, Mahsan Rofouei, M. Sarrafzadeh","doi":"10.1109/ISQED.2008.161","DOIUrl":"https://doi.org/10.1109/ISQED.2008.161","url":null,"abstract":"Power and energy consumption has emerged as the premier and most constraining aspect in modern computational systems. Dynamic voltage scheduling (DVS) has been provably one of the most effective techniques used to achieve low power specification. On the other hand, as the feature size of logic gates (and transistors) is becoming smaller and smaller, the effect of soft error rates caused by single event upsets (SEUs) becomes exponentially greater. Lowering supply voltage to save energy increases soft error rates caused by SEU for two reasons: I) lower voltage makes digital circuits more prone to soft errors and II) reduction in supply voltage, increases the duration of process which increases the chances of being hit by SEU. In this paper, we propose an optimal methodology for DVS on a task graph with consideration of soft error rate. We consider the effects of voltage on SEU and incorporate this dependency in our formulation to develop a new method for energy optimization under SEU constraints. We also propose a convex programming formulation that can be solved efficiently and optimally. We show the effectiveness of our optimal results by simulation on TGFF benchmarks.","PeriodicalId":243121,"journal":{"name":"9th International Symposium on Quality Electronic Design (isqed 2008)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128840544","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 31

Robust Estimation of Timing Yield with Partial Statistical Information on Process Variations 含工艺变化部分统计信息的定时良率鲁棒估计

9th International Symposium on Quality Electronic Design (isqed 2008) Pub Date : 2008-03-17 DOI: 10.1109/ISQED.2008.104

Lin Xie, A. Davoodi

引用次数: 3

Tutorial 1: The Promise of High-k/Metal Gates-From Electronic Transport Phenomena to Emerging Device/Circuit Applications 第1课:高k/金属门的前景——从电子输运现象到新兴器件/电路应用

9th International Symposium on Quality Electronic Design (isqed 2008) Pub Date : 2008-03-17 DOI: 10.1109/ISQED.2008.172

K. Maitra

引用次数: 0