Proceedings of the 20th International Workshop on Software and Compilers for Embedded Systems最新文献

Exploiting Predictability in Dynamic Network Communication for Power-Efficient Data Transmission in LTE Radio Systems 在LTE无线电系统中利用动态网络通信的可预测性实现高能效数据传输

Proceedings of the 20th International Workshop on Software and Compilers for Embedded Systems Pub Date : 2017-06-12 DOI: 10.1145/3078659.3078670

Peter Brand, Jonathan Ah Sue, J. Brendel, J. Falk, R. Hasholzner, Jürgen Teich, S. Wildermann

{"title":"Exploiting Predictability in Dynamic Network Communication for Power-Efficient Data Transmission in LTE Radio Systems","authors":"Peter Brand, Jonathan Ah Sue, J. Brendel, J. Falk, R. Hasholzner, Jürgen Teich, S. Wildermann","doi":"10.1145/3078659.3078670","DOIUrl":"https://doi.org/10.1145/3078659.3078670","url":null,"abstract":"In embedded systems powered by batteries, power is undoubtedly a critical resource making power management an important topic in the design phase. Even though power management is a heavily researched topic, most approaches focus on improving the way the power manager reacts to outside control events. In this paper, we propose techniques that not only react but rather try to predict these outside control events in advance, thus, broadening the capabilities of any employed power manager by allowing for superior transition decisions and even saving redundant calculations. We present results on employing a predictive power management system that couples a classic dynamic power manager with a machine learning subsystem in the context of a mobile device in a Long Term Evolution (LTE) system, with emphasis on evaluating the potential of saving power as well as the handling of the induced prediction uncertainty. First, we examine the LTE communication protocol and showcase certain control data that has to be received periodically, but may contain no information for the receiver. Finally, we show a proof-of-concept based on real LTE traces and hardware simulation, that prediction of this information can be leveraged to allow for a far superior decision process compared to a non-predicting system. Here, we achieve a theoretical best case power saving of 15 % for an idealized prediction with 100 % accuracy and no additional power consumption.","PeriodicalId":240210,"journal":{"name":"Proceedings of the 20th International Workshop on Software and Compilers for Embedded Systems","volume":"193 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126046736","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

TETRiS: a Multi-Application Run-Time System for Predictable Execution of Static Mappings 俄罗斯方块:用于可预测执行静态映射的多应用运行时系统

Proceedings of the 20th International Workshop on Software and Compilers for Embedded Systems Pub Date : 2017-06-12 DOI: 10.1145/3078659.3078663

Andrés Goens, R. Khasanov, J. Castrillón, Marcus Hähnel, Till Smejkal, Hermann Härtig

引用次数: 28

Combining Dataflow Applications and Real-time Task Sets on Multi-core Platforms 在多核平台上结合数据流应用和实时任务集

Proceedings of the 20th International Workshop on Software and Compilers for Embedded Systems Pub Date : 2017-06-12 DOI: 10.1145/3078659.3078671

H. Ali, B. Akesson, L. M. Pinho

{"title":"Combining Dataflow Applications and Real-time Task Sets on Multi-core Platforms","authors":"H. Ali, B. Akesson, L. M. Pinho","doi":"10.1145/3078659.3078671","DOIUrl":"https://doi.org/10.1145/3078659.3078671","url":null,"abstract":"Future real-time embedded systems will increasingly incorporate mixed application models with timing constraints running on the same multi-core platform. These application models are dataflow applications with timing constraints and traditional real-time applications modelled as independent arbitrary-deadline tasks. These systems require guarantees that all running applications execute satisfying their timing constraints. Also, to be cost-efficient in terms of design, they require efficient mapping strategies that maximize the use of system resources to reduce the overall cost. This work proposes an approach to integrate mixed application models (dataflow and traditional real-time applications) with timing requirements on the same multi-core platform. It comprises three main algorithms: 1) Slack-Based Merging, 2) Timing Parameter Extraction, and 3) Communication-Aware Mapping. Together, these three algorithms play a part in allowing mapping and scheduling of mixed application models in embedded real-time systems. The complete approach and the three algorithms presented have been validated through proofs and experimental evaluation.","PeriodicalId":240210,"journal":{"name":"Proceedings of the 20th International Workshop on Software and Compilers for Embedded Systems","volume":"125 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134283656","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Enabling zero-copy OpenMP offloading on the PULP many-core accelerator 在PULP多核加速器上启用零拷贝OpenMP卸载

Proceedings of the 20th International Workshop on Software and Compilers for Embedded Systems Pub Date : 2017-06-12 DOI: 10.1145/3078659.3079071

Alessandro Capotondi, A. Marongiu

引用次数: 5

Stencil Autotuning with Ordinal Regression: Extended Abstract 基于有序回归的模板自调整:扩展摘要

Proceedings of the 20th International Workshop on Software and Compilers for Embedded Systems Pub Date : 2017-06-12 DOI: 10.1145/3078659.3078664

Biagio Cosenza, J. Durillo, Stefano Ermon, B. Juurlink

{"title":"Stencil Autotuning with Ordinal Regression: Extended Abstract","authors":"Biagio Cosenza, J. Durillo, Stefano Ermon, B. Juurlink","doi":"10.1145/3078659.3078664","DOIUrl":"https://doi.org/10.1145/3078659.3078664","url":null,"abstract":"The increasing performance of today's computer architecture comes with an unprecedented augment of hardware complexity. Unfortunately this results in difficult-to-tune software and consequentially in a gap between the potential peak performance and the actual performance. Automatic tuning is an emerging approach that assists the programmer in managing this complexity. State-of-the-art autotuners are limited, though: they either require long tuning times, e.g., due to iterative searches, or cannot tackle the complexity of the problem due to the limitation of the supervised machine learning (ML) methodologies used. In particular, traditional ML autotuning approaches exploiting classification algorithms (such as neural networks and support vector machines) face difficulties in capturing all features of large search spaces. We propose a new way of performing automatic tuning based on structural learning: the tuning problem is formulated as a version ranking prediction modeling and solved using ordinal regression. We demonstrate its potential on a well-known autotuning problem: stencil computations. We compare state-of-the-art iterative compilation methods with our ordinal regression approach and analyze the quality of the obtained ranking in terms of Kendall rank correlation coefficients.","PeriodicalId":240210,"journal":{"name":"Proceedings of the 20th International Workshop on Software and Compilers for Embedded Systems","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133150349","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Numerical Accuracy Improvement by Interprocedural Program Transformation 程序间程序转换提高数值精度

Proceedings of the 20th International Workshop on Software and Compilers for Embedded Systems Pub Date : 2017-06-12 DOI: 10.1145/3078659.3078662

Nasrine Damouche, M. Martel, Alexandre Chapoutot

引用次数: 6

Self-Adaptive FPGA-Based Image Processing Filters Using Approximate Arithmetics 基于近似算法的自适应fpga图像处理滤波器

Proceedings of the 20th International Workshop on Software and Compilers for Embedded Systems Pub Date : 2017-06-12 DOI: 10.1145/3078659.3078669

Jutta Pirkl, Andreas Becher, Jorge Echavarria, J. Teich, S. Wildermann

引用次数: 2

Robust Mapping of Process Networks to Many-Core Systems using Bio-Inspired Design Centering 基于仿生设计中心的过程网络多核系统鲁棒映射

Proceedings of the 20th International Workshop on Software and Compilers for Embedded Systems Pub Date : 2017-06-12 DOI: 10.1145/3078659.3078667

G. Hempel, Andrés Goens, J. Castrillón, Josefine Asmus, I. Sbalzarini

{"title":"Robust Mapping of Process Networks to Many-Core Systems using Bio-Inspired Design Centering","authors":"G. Hempel, Andrés Goens, J. Castrillón, Josefine Asmus, I. Sbalzarini","doi":"10.1145/3078659.3078667","DOIUrl":"https://doi.org/10.1145/3078659.3078667","url":null,"abstract":"Embedded systems are often designed as complex architectures with numerous processing elements. Effectively programming such systems requires parallel programming models e.g. task-based or dataflow-based models. With these types of models, the mapping of the abstract application model to the existing hardware architecture plays a decisive role and is usually optimized to achieve an ideal resource footprint or a near-minimal execution time. However, when mapping several independent programs to the same platform, resource conflicts can arise. This can be circumvented by remapping some of the tasks of an application, which in turn affect its timing behavior, possibly leading to constraint violations. In this work we present a novel method to compute mappings that are robust against local task remapping. The underlying method is based on the bio-inspired design centering algorithm of Lp-Adaptation. We evaluate this with several benchmarks on different platforms and show that mappings obtained with our algorithm are indeed robust. In all experiments, our robust mappings tolerated significantly more run-time perturbations without violating constraints than mappings devised with optimization heuristics","PeriodicalId":240210,"journal":{"name":"Proceedings of the 20th International Workshop on Software and Compilers for Embedded Systems","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134019251","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

On the Accuracy of Near-Optimal GPU-Based Path Planning for UAVs 基于gpu的无人机近最优路径规划精度研究

Proceedings of the 20th International Workshop on Software and Compilers for Embedded Systems Pub Date : 2017-06-12 DOI: 10.1145/3078659.3079072

D. Palossi, A. Marongiu, L. Benini

引用次数: 1

Automatic Conversion of Simulink Models to SysteMoC Actor Networks Simulink模型到systememoc参与者网络的自动转换

Proceedings of the 20th International Workshop on Software and Compilers for Embedded Systems Pub Date : 2017-06-12 DOI: 10.1145/3078659.3078668

Martín Letras, J. Falk, S. Wildermann, J. Teich

{"title":"Automatic Conversion of Simulink Models to SysteMoC Actor Networks","authors":"Martín Letras, J. Falk, S. Wildermann, J. Teich","doi":"10.1145/3078659.3078668","DOIUrl":"https://doi.org/10.1145/3078659.3078668","url":null,"abstract":"Simulink has gained a lot of acceptance due to its intuitive through block-based algorithm design, simulation, and rapid prototyping capabilities for signal processing as well as control applications. However, automatic code generation for heterogeneous architectures is currently not supported by Simulink. In the literature, there exist automatic translation toolchains for generation of C or C++ code from Simulink models, which then are used for implementation or validation purposes. But few of them approach the generation of models that can be used in well-established Electronic System Level (ESL) design methodologies and tools. In order to address this issue, we present a methodology to extract an executable specification based on Data Flow Graphs (DFGs) from a given Simulink model. Such a specification can then be used by ESL tools to perform a Design Space Exploration (DSE) and generate code for hardware/software partitions directly from the ESL model. In a case study from signal processing, we validate the equivalence of the results of the simulation in Simulink and the results obtained by simulation of the DFG fully automatically generated from the Simulink model in the SystemC-based actor language SysteMoC.","PeriodicalId":240210,"journal":{"name":"Proceedings of the 20th International Workshop on Software and Compilers for Embedded Systems","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124428094","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6