Proceedings of the 20th International Workshop on Software and Compilers for Embedded Systems最新文献_第2页

Hybrid Latency Minimization Approach using Model Checking and Dataflow Analysis 基于模型检验和数据流分析的混合延迟最小化方法

Proceedings of the 20th International Workshop on Software and Compilers for Embedded Systems Pub Date : 2017-06-12 DOI: 10.1145/3078659.3078665

G. Kuiper, P. Kurtin, M. Bekooij

{"title":"Hybrid Latency Minimization Approach using Model Checking and Dataflow Analysis","authors":"G. Kuiper, P. Kurtin, M. Bekooij","doi":"10.1145/3078659.3078665","DOIUrl":"https://doi.org/10.1145/3078659.3078665","url":null,"abstract":"Bounding the latency of real-time multiprocessor applications is crucial for safety-critical systems. Several approximative analysis approaches exist that can efficiently analyze the latency. However, these approaches produce pessimistic latency results and do not exploit buffer sizing nor exploit additional sequence constraints to reduce the latency. More accurate latency analysis results can be obtained using model checking of timed-automata, however, at the cost of a typically excessive run-time. This paper presents a latency analysis approach for cyclic task graphs using model checking of timed automata of which the run-time is reduced. The approach is applicable for systems in which tasks are executed on shared processors using a Fixed Priority Pre-emptive (FPP) scheduling policy. The reduction in run-time is achieved by pruning the search space of options that need to be analyzed using the model checker by making use of approximative dataflow analysis techniques. The approach exploits dimensioning of buffers to minimize interference and latency. Moreover, sequence constraints are introduced and automatically adapted in order to minimize the latency of the task graph. A WLAN 802.11p transceiver application is used in the case study to compare this hybrid analysis approach to a state-of-the-art approximation based approach that uses iterative buffer sizing. Using our approach, the analyzed latency decreased from 17 μs to 15 μs at the cost of a run-time of 23 minutes instead of a fraction of a second.","PeriodicalId":240210,"journal":{"name":"Proceedings of the 20th International Workshop on Software and Compilers for Embedded Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131171953","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Constructing HPSSA over SSA 构建基于SSA的HPSSA

Proceedings of the 20th International Workshop on Software and Compilers for Embedded Systems Pub Date : 2017-06-12 DOI: 10.1145/3078659.3078660

Smriti Jaiswal, P. Hegde, Subhajit Roy

{"title":"Constructing HPSSA over SSA","authors":"Smriti Jaiswal, P. Hegde, Subhajit Roy","doi":"10.1145/3078659.3078660","DOIUrl":"https://doi.org/10.1145/3078659.3078660","url":null,"abstract":"The Hot Path SSA (HPSSA) form filled a long-standing void by providing an SSA-like intermediate representation that could weave static program code and run-time profile information in a single data structure, thereby facilitating speculative analyses and optimizations. The original algorithm proposed for the Hot Path SSA construction builds HPSSA over non-SSA programs with interleaved SSA and HPSSA construction passes. In this work, we propose a new algorithm for constructing HPSSA programs from programs in the SSA form. Our new algorithm has the following advantages over the original algorithm: firstly, as all modern compilers have built-in SSA construction passes, it is difficult to incorporate the original algorithm within an existing compiler as it requires the compiler writer to intrude in and retrofit the HPSSA construction stages with the SSA construction pass. Our new algorithm can simply be pipelined next to the SSA construction pass with no modification required to existing passes. Secondly, our new algorithm is more efficient than the original algorithm: the original algorithm needs to process all definitions in the program while our new algorithm processes only the φ-functions---a small fraction of all program instructions. Most importantly, our new algorithm is much simpler than the original algorithm. We have implemented our algorithm in the LLVM compiler framework and evaluated its effectiveness by implementing an ILP driven path-profile guided register allocator.","PeriodicalId":240210,"journal":{"name":"Proceedings of the 20th International Workshop on Software and Compilers for Embedded Systems","volume":"105 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117221541","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

The LPGPU2 Project: Low-Power Parallel Computing on GPUs: Extended Abstract LPGPU2项目:gpu上的低功耗并行计算:扩展摘要

Proceedings of the 20th International Workshop on Software and Compilers for Embedded Systems Pub Date : 2017-06-12 DOI: 10.1145/3078659.3078672

B. Juurlink, J. Lucas, Nadjib Mammeri, Martyn Bliss, G. Keramidas, Chrysa Kokkala, A. Richards

引用次数: 2

Data Dependent Energy Modeling for Worst Case Energy Consumption Analysis 基于数据的最坏情况能耗分析模型

Proceedings of the 20th International Workshop on Software and Compilers for Embedded Systems Pub Date : 2015-05-13 DOI: 10.1145/3078659.3078666

James Pallister, Steve Kerrison, J. Morse, K. Eder

引用次数: 17

Proceedings of the 20th International Workshop on Software and Compilers for Embedded Systems 第20届嵌入式系统软件与编译器国际研讨会论文集

Proceedings of the 20th International Workshop on Software and Compilers for Embedded Systems Pub Date : 1900-01-01 DOI: 10.1145/3078659

引用次数: 0