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2014 IEEE 5th Latin American Symposium on Circuits and Systems最新文献

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New CMOS realization of Current Differencing Current Conveyor (CDCC) with biquad filter application 采用双滤波器的差动电流输送机(CDCC)的新型CMOS实现
2014 IEEE 5th Latin American Symposium on Circuits and Systems Pub Date : 2014-05-26 DOI: 10.1109/LASCAS.2014.6820248
F. Kaçar, A. Ismail, H. Kuntman
{"title":"New CMOS realization of Current Differencing Current Conveyor (CDCC) with biquad filter application","authors":"F. Kaçar, A. Ismail, H. Kuntman","doi":"10.1109/LASCAS.2014.6820248","DOIUrl":"https://doi.org/10.1109/LASCAS.2014.6820248","url":null,"abstract":"In this paper, a new CMOS realization of Current Differencing Current Conveyor (CDCC) is proposed. Furthermore, to demonstrate the performance of the CMOS circuit, a new biquad filter configuration is introduced employing a single CDCC and four passive components. The proposed filter has three-inputs, a single-output and realizes current-mode low-pass, band-pass, high-pass, and band-stop filter functions. The biquad filters realizing these filter functions are simulated using TSMC CMOS 0.35 μm technology. PSPICE simulation results agree well with the theoretical analysis.","PeriodicalId":235336,"journal":{"name":"2014 IEEE 5th Latin American Symposium on Circuits and Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2014-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125772321","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Form factor improvement of smart-pixels for vision sensors through 3-D vertically-integrated technologies 利用三维垂直集成技术改进视觉传感器智能像素的外形尺寸
2014 IEEE 5th Latin American Symposium on Circuits and Systems Pub Date : 2014-05-26 DOI: 10.1109/LASCAS.2014.6820327
Á. Rodríguez-Vázquez, R. Carmona-Galán, J. Fernández-Berni, S. Vargas-Sierra, J. A. Leñero-Bardallo, Manuel Suárez-Cambre, V. Brea, Maria Belen Pérez-Verdú
{"title":"Form factor improvement of smart-pixels for vision sensors through 3-D vertically-integrated technologies","authors":"Á. Rodríguez-Vázquez, R. Carmona-Galán, J. Fernández-Berni, S. Vargas-Sierra, J. A. Leñero-Bardallo, Manuel Suárez-Cambre, V. Brea, Maria Belen Pérez-Verdú","doi":"10.1109/LASCAS.2014.6820327","DOIUrl":"https://doi.org/10.1109/LASCAS.2014.6820327","url":null,"abstract":"While conventional CMOS active pixel sensors embed only the circuitry required for photo-detection, pixel addressing and voltage buffering, smart pixels incorporate also circuitry for data processing, data storage and control of data interchange. This additional circuitry enables data processing be realized concurrently with the acquisition of images which is instrumental to reduce the number of data needed to carry to information contained into images. This way, more efficient vision systems can be built at the cost of larger pixel pitch. Vertically-integrated 3D technologies enable to keep the advnatges of smart pixels while improving the form factor of smart pixels.","PeriodicalId":235336,"journal":{"name":"2014 IEEE 5th Latin American Symposium on Circuits and Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2014-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126125569","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Behavioral modelling of a 4th order LP ΣΔ modulator-towards the design of a hybrid proposal 四阶LP ΣΔ调制器的行为建模——迈向混合方案的设计
2014 IEEE 5th Latin American Symposium on Circuits and Systems Pub Date : 2014-05-26 DOI: 10.1109/LASCAS.2014.6820297
J. G. García-Sánchez, D. Calderón-Preciado, F. Sandoval-Ibarra, J. M. Rosa
{"title":"Behavioral modelling of a 4th order LP ΣΔ modulator-towards the design of a hybrid proposal","authors":"J. G. García-Sánchez, D. Calderón-Preciado, F. Sandoval-Ibarra, J. M. Rosa","doi":"10.1109/LASCAS.2014.6820297","DOIUrl":"https://doi.org/10.1109/LASCAS.2014.6820297","url":null,"abstract":"Hybrid ΣΔ modulator has the property of take advantage of the capabilities of CT and DT architectures and is thus very effective in the cascade approach. In this paper, we show the behavioral simulation of ΣΔ modulators in SIMSIDES. A set of experiments based on models for analyzing the overall performance of SC ΣΔ modulators were used in order to translate design considerations into a set of values such that the design at transistor level be established by the desired performance of the proposed architecture. This design methodology is not the most accurate but it allows the designer to get a general comprehension of the system under design, a comprehension at the highest level of abstraction. The system under study is a cascade 4th order hybrid ΣΔ modulator, from which the second stage is a 2nd order Low-Pass (LP) DT ΣΔ modulator. The ideal behavioral performance of the DT modulator is used as vehicle to show how non-idealities must be taken into account, and also how to translate design considerations into a set of physical values for designing building blocks at transistor level.","PeriodicalId":235336,"journal":{"name":"2014 IEEE 5th Latin American Symposium on Circuits and Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2014-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124737665","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A comparison of high-efficiency UHF RFID rectifiers using internal voltage compensation and zero-threshold-voltage MOSFETs 采用内部电压补偿和零阈值电压mosfet的高效率UHF RFID整流器的比较
2014 IEEE 5th Latin American Symposium on Circuits and Systems Pub Date : 2014-05-26 DOI: 10.1109/LASCAS.2014.6820301
M. Matias, J. P. Cunha, P. A. D. Fabbro, D. Mioni, W. Prodanov, M. Pessatti, B. Leite, A. Mariano
{"title":"A comparison of high-efficiency UHF RFID rectifiers using internal voltage compensation and zero-threshold-voltage MOSFETs","authors":"M. Matias, J. P. Cunha, P. A. D. Fabbro, D. Mioni, W. Prodanov, M. Pessatti, B. Leite, A. Mariano","doi":"10.1109/LASCAS.2014.6820301","DOIUrl":"https://doi.org/10.1109/LASCAS.2014.6820301","url":null,"abstract":"This paper discusses and compares the design of two high-efficiency 4-stage voltage-doubler UHF RFID rectifier operating at 915 MHz. The first rectifier uses conventional 180-nm CMOS transistors applying a technique of internal cancellation in order to compensate the high value of their threshold voltages (Vth). The second proposed rectifier uses zero-Vth transistors, which are available in a 130 nm CMOS process, eliminating the need for compensation circuitry. The circuit implementing Vth compensation occupies a 0.025 mm2 area, achieving a -12 dBm input sensitivity and a 18% power conversion efficiency (PCE) when supplying a 1.2 V output voltage and a 10 μA load current. For the same load conditions, the circuit including zero-Vth transistors presents a reduced area occupation (0.013 mm2), while providing both improved sensitivity (-14.3 dBm) and a 33% PCE at this sensitivity.","PeriodicalId":235336,"journal":{"name":"2014 IEEE 5th Latin American Symposium on Circuits and Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2014-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121313088","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
Two-dimensional analog filtering and its implications on circuit theory 二维模拟滤波及其对电路理论的影响
2014 IEEE 5th Latin American Symposium on Circuits and Systems Pub Date : 2014-05-26 DOI: 10.1109/LASCAS.2014.6820262
S. Erfani, M. Ahmadi, N. Bayan
{"title":"Two-dimensional analog filtering and its implications on circuit theory","authors":"S. Erfani, M. Ahmadi, N. Bayan","doi":"10.1109/LASCAS.2014.6820262","DOIUrl":"https://doi.org/10.1109/LASCAS.2014.6820262","url":null,"abstract":"The objective of this paper is to focus on two-dimensional (2-D) analog linear systems. The potential of many 2-D concepts in analog domain have not been explored properly. Techniques of MDLT, in general, and 2DLT in particular, make it possible to characterize a large class of nonlinear analytic systems and the entire analog linear time-varying (LTV) systems and circuits including the entire communication networks. In this paper the development of a bifrequency theory for autonomous dynamic systems is outlined. The paper complements contents of existing literature more than duplicate.","PeriodicalId":235336,"journal":{"name":"2014 IEEE 5th Latin American Symposium on Circuits and Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2014-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130737378","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Hardware implementation of the Smith-Waterman algorithm using a systolic architecture 使用收缩架构的Smith-Waterman算法的硬件实现
2014 IEEE 5th Latin American Symposium on Circuits and Systems Pub Date : 2014-05-26 DOI: 10.1109/LASCAS.2014.6820284
J. M. Marmolejo-Tejada, V. Trujillo-Olaya, Claudia Patricia Renteria-Mejia, Jaime Velasco-Medina
{"title":"Hardware implementation of the Smith-Waterman algorithm using a systolic architecture","authors":"J. M. Marmolejo-Tejada, V. Trujillo-Olaya, Claudia Patricia Renteria-Mejia, Jaime Velasco-Medina","doi":"10.1109/LASCAS.2014.6820284","DOIUrl":"https://doi.org/10.1109/LASCAS.2014.6820284","url":null,"abstract":"This paper presents the design of a systolic processor for DNA local pairwise alignment. The main building block of the processor is a 1D array of processing elements that allows pipeline processing to reduce the execution time with respect to software tools. We aligned two sequences of 4096 nucleotides from the ABO blood group gene of human and house mouse using ModelSim-Altera to verify the hardware design. The hardware simulation results were compared with software simulation results, showing the functionality of the design. The design can only be synthesized on the targeted FPGA for processing 256 nucleotides simultaneously due to hardware limitations (ALUTs and registers), but could be implemented for aligning larger sequences by using a bigger device or FPGA arrays. The design could also be used to implement other dynamic programming algorithms by modifying the processing element.","PeriodicalId":235336,"journal":{"name":"2014 IEEE 5th Latin American Symposium on Circuits and Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2014-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114340567","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Comparison of conventional and new class AB modifications of the Flipped Voltage Follower and their implementation in high performance amplifiers 翻转电压从动器的传统和新型AB类改进的比较及其在高性能放大器中的实现
2014 IEEE 5th Latin American Symposium on Circuits and Systems Pub Date : 2014-05-26 DOI: 10.1109/LASCAS.2014.6820312
I. Padilla-Cantoya, F. Silva-Del-Rosario, Miguel Silva-Martinez, J. E. Molinar-Solís
{"title":"Comparison of conventional and new class AB modifications of the Flipped Voltage Follower and their implementation in high performance amplifiers","authors":"I. Padilla-Cantoya, F. Silva-Del-Rosario, Miguel Silva-Martinez, J. E. Molinar-Solís","doi":"10.1109/LASCAS.2014.6820312","DOIUrl":"https://doi.org/10.1109/LASCAS.2014.6820312","url":null,"abstract":"A comparison between different modifications of the conventional cell denominated as Flipped Voltage Follower to provide class AB operation is presented. Additionally, two new class-AB structures with high linearity and large operational range are introduced, and included in the comparison. Computer simulation shows the operation of these modifications when driving a capacitive load, including the resulting output resistance when the class AB operation is achieved. Also, the implementation of these modifications in a highly linear operational transconductance amplifier is discussed, as well as the impact of the output resistance of these modifications on the linearity of the system. Additionally, a variation of conventional cascoded current mirrors used in the amplifier to achieve very large output currents is presented. Simulation results in 0.5μm technology show the results of the comparison.","PeriodicalId":235336,"journal":{"name":"2014 IEEE 5th Latin American Symposium on Circuits and Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2014-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115249645","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Parallel vs. serial inter-plane communication using TSVs 使用tsv的并行与串行平面间通信
2014 IEEE 5th Latin American Symposium on Circuits and Systems Pub Date : 2014-05-26 DOI: 10.1109/LASCAS.2014.6820325
S. R. Omam, Y. Leblebici, G. Micheli
{"title":"Parallel vs. serial inter-plane communication using TSVs","authors":"S. R. Omam, Y. Leblebici, G. Micheli","doi":"10.1109/LASCAS.2014.6820325","DOIUrl":"https://doi.org/10.1109/LASCAS.2014.6820325","url":null,"abstract":"3-D integration is a promising prospect for implementing high performance multifunctional systems-on-chip. Through Silicon Vias (TSVs) are the enablers for achieving high bandwidth paths in inter-plane communications. TSVs also provide higher vertical link density and facilitate the heat flow in the 3-D circuits as compared to other potential schemes such as inductive links. However, reliability issues and crosstalk problems among adjacent TSVs decrease the yield and performance of TSV based circuits. Reducing the number of TSVs employed for inter-plane signal transferring can alleviate these problems. This paper proposes to exploit serialization to reduce the number of TSVs in a 3D circuit and presents a comparison between different aspects of TSV-based 3-D circuits such as area, power, crosstalk and yield in parallel and serial vertical links.","PeriodicalId":235336,"journal":{"name":"2014 IEEE 5th Latin American Symposium on Circuits and Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2014-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120868965","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Comparing high-performance cells in CMOS bulk and FinFET technologies 比较CMOS体和FinFET技术中的高性能电池
2014 IEEE 5th Latin American Symposium on Circuits and Systems Pub Date : 2014-05-26 DOI: 10.1109/LASCAS.2014.6820310
C. Meinhardt, R. Reis
{"title":"Comparing high-performance cells in CMOS bulk and FinFET technologies","authors":"C. Meinhardt, R. Reis","doi":"10.1109/LASCAS.2014.6820310","DOIUrl":"https://doi.org/10.1109/LASCAS.2014.6820310","url":null,"abstract":"Technology evolution brings new challenges to integrated circuits (IC) design. Parameter variation and complex design rules demand a great effort to create suitable design approaches to ensure manufacturability. Regular layout techniques allow a more accurate estimate of the circuit power and delay in early design steps. In this context, this work presents an evaluation of a set of basic cells candidates to integrate a 32nm high performance cell library in a regular layout synthesis flow. Considering a delay optimization flow, Inverters, NAND2 and NOR2 gates in CMOS bulk technology have shown better dynamic and static power results, when compared with predictive FinFET technologies.","PeriodicalId":235336,"journal":{"name":"2014 IEEE 5th Latin American Symposium on Circuits and Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2014-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128511596","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A 1.6Gb/s CMOS LVDS transmitter with a programmable pre-emphasis system 1.6Gb/s CMOS LVDS变送器，具有可编程预强调系统
2014 IEEE 5th Latin American Symposium on Circuits and Systems Pub Date : 2014-05-26 DOI: 10.1109/LASCAS.2014.6820268
Benjamín T. Reyes, German Paulina, L. Tealdi, Emanuel Labat, R. Sanchez, P. Mandolesi, M. Hueda
{"title":"A 1.6Gb/s CMOS LVDS transmitter with a programmable pre-emphasis system","authors":"Benjamín T. Reyes, German Paulina, L. Tealdi, Emanuel Labat, R. Sanchez, P. Mandolesi, M. Hueda","doi":"10.1109/LASCAS.2014.6820268","DOIUrl":"https://doi.org/10.1109/LASCAS.2014.6820268","url":null,"abstract":"A 12 parallel low voltage differential signaling (LVDS) transmitter fabricated in 0.13 μm CMOS is presented. Each LVDS channel can operate over 1.6 Gb/s and includes a programmable pre-emphasis circuit designed to reduce the data-dependent jitter (DDJ) caused by different lengths of PCB traces. Experimental results of the fabricated LVDS confirm the correct operation of the programmable pre-equalization circuit. The power consumption and area per channel is less than 20 mW and 0.084 mm2, respectively.","PeriodicalId":235336,"journal":{"name":"2014 IEEE 5th Latin American Symposium on Circuits and Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2014-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134345718","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
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