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2014 IEEE 5th Latin American Symposium on Circuits and Systems最新文献

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An adaptable CMOS depressing synapse with detection of changes in input spike rate 一种能检测输入尖峰速率变化的自适应CMOS抑制突触
2014 IEEE 5th Latin American Symposium on Circuits and Systems Pub Date : 2014-05-26 DOI: 10.1109/LASCAS.2014.6820322
Yilda Irizarry-Valle, A. C. Parker, N. Grzywacz
{"title":"An adaptable CMOS depressing synapse with detection of changes in input spike rate","authors":"Yilda Irizarry-Valle, A. C. Parker, N. Grzywacz","doi":"10.1109/LASCAS.2014.6820322","DOIUrl":"https://doi.org/10.1109/LASCAS.2014.6820322","url":null,"abstract":"Sensory pathways in the brain attain large dynamic ranges and novelty detection through adaptive mechanisms. We present a CMOS neuromorphic circuit emulating the adaptation dynamics of short-term depressing synapses for both transient and steady state. The circuit detects abrupt changes in the input firing rate following the Weber-Fechner relation, where the transient response is proportional to the fractional change of the input firing rate. In the steady state, the input-output relationship follows the one over frequency law in the excitatory postsynaptic potential (EPSP) amplitude. The circuit also detects novel change after a long interval of inactivity. The design comprises a small number of transistors, while capturing the desired input-output relationship. The amplitude of both transient and steady state EPSP are tunable. To our knowledge this is the first CMOS design to approach the Weber-Fechner relation.","PeriodicalId":235336,"journal":{"name":"2014 IEEE 5th Latin American Symposium on Circuits and Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2014-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124885467","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Dynamic gate-level body biasing for subthreshold digital design 门限下数字设计的动态门级体偏置
2014 IEEE 5th Latin American Symposium on Circuits and Systems Pub Date : 2014-05-26 DOI: 10.1109/LASCAS.2014.6820278
M. Lanuzza, R. Taco, D. Albano
{"title":"Dynamic gate-level body biasing for subthreshold digital design","authors":"M. Lanuzza, R. Taco, D. Albano","doi":"10.1109/LASCAS.2014.6820278","DOIUrl":"https://doi.org/10.1109/LASCAS.2014.6820278","url":null,"abstract":"Dynamic gate-level body biasing has been recently proposed as an alternative design methodology for subthreshold logic gates. According to this approach, a simple body biasing circuit, embedded in the logic gate, is exploited to change dynamically the threshold voltage of transistors on the basis of the gate status. This allows fast gate switching, while maintaining high energy efficiency. In this work, the proposed technique is exploited to design a low voltage mirror full-adder. When implemented in a 45 nm commercial technology, the designed circuit is 2 and 1.3 times faster than its standard CMOS and DTMOS counterparts. This is achieved while maintaining the lowest total energy per operation consumption and robustness against temperature and process variations.","PeriodicalId":235336,"journal":{"name":"2014 IEEE 5th Latin American Symposium on Circuits and Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2014-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130105887","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Detailing a useful position calibration for microphone arrays 详细介绍了麦克风阵列的有用位置校准
2014 IEEE 5th Latin American Symposium on Circuits and Systems Pub Date : 2014-05-26 DOI: 10.1109/LASCAS.2014.6820266
Darwin M. Paredes-Calderon, J. A. Apolinário
{"title":"Detailing a useful position calibration for microphone arrays","authors":"Darwin M. Paredes-Calderon, J. A. Apolinário","doi":"10.1109/LASCAS.2014.6820266","DOIUrl":"https://doi.org/10.1109/LASCAS.2014.6820266","url":null,"abstract":"This paper details a simple and useful method for obtaining sensor coordinates in a microphone array. The scheme described herein is based on a well known technique, the multidimensional scaling, which uses distances measured between pairs of microphones to estimate their coordinates in a three dimensional space. While the classical multidimensional scaling provides a solution having the same set of distances (as the provided inputs) but with an arbitrary rotation, this work uses array previous information to obtain the least error among the estimated coordinates and the actual array. The previous information is related to the assumption that we know the nominal coordinates and to the fact that, when in field operation, the array is aligned properly. An error performance analysis is carried out for spatial arrays of four and seven microphones.","PeriodicalId":235336,"journal":{"name":"2014 IEEE 5th Latin American Symposium on Circuits and Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2014-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127127314","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Design of RF BAW-based ΣΔ Modulators 基于射频baw的ΣΔ调制器设计
2014 IEEE 5th Latin American Symposium on Circuits and Systems Pub Date : 2014-05-26 DOI: 10.1109/LASCAS.2014.6820294
D. Belfort, S. Catunda, H. Aboushady
{"title":"Design of RF BAW-based ΣΔ Modulators","authors":"D. Belfort, S. Catunda, H. Aboushady","doi":"10.1109/LASCAS.2014.6820294","DOIUrl":"https://doi.org/10.1109/LASCAS.2014.6820294","url":null,"abstract":"Analysis of the Bulk Acoustic Wave (BAW) resonator modeled as a two-port device is presented for applications in Sigma Delta Modulator (ΣΔM) based Analog-to-Digital Converter (ADC). The design of BAW-based Continuous Time (CT) ΣΔM starting from a Discrete Time (DT) model, which is designed from scratch, is presented and explained in details. In order to convert a DT ΣΔM into CT BAW-based ΣΔM, Finite Impulse Response (FIR) filters are used in the feedback path increasing the degrees of freedom. We discuss and validate the calculation of the FIR filter coefficients by using a design example of BAW-based ΣΔMs.","PeriodicalId":235336,"journal":{"name":"2014 IEEE 5th Latin American Symposium on Circuits and Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2014-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126247940","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
0.9 V, 5 nW, 9 ppm/oC resistorless sub-bandgap voltage reference in 0.18μm CMOS 0.9 V, 5 nW, 9 ppm/oC, 0.18μm CMOS无电阻子带隙基准电压
2014 IEEE 5th Latin American Symposium on Circuits and Systems Pub Date : 2014-05-26 DOI: 10.1109/LASCAS.2014.6820273
O. E. Mattia, H. Klimach, S. Bampi
{"title":"0.9 V, 5 nW, 9 ppm/oC resistorless sub-bandgap voltage reference in 0.18μm CMOS","authors":"O. E. Mattia, H. Klimach, S. Bampi","doi":"10.1109/LASCAS.2014.6820273","DOIUrl":"https://doi.org/10.1109/LASCAS.2014.6820273","url":null,"abstract":"In this work a novel resistorless sub-bandgap voltage reference (BGR) is introduced. It is a self-biased and small area topology that works in the nano-ampere current consumption range, and under 1 V of power supply. The analytical behavior of the circuit is described, and simulation results for a standard 0.18 μm CMOS process are analysed. A reference voltage of 479 mV is demonstrated, with a temperature coefficient of 8.79 ppm/°C for the 0 to 125°C range, while the power consumption of the whole circuit is 4.86 nW under a 0.9 V power supply at 27 oC. The estimated silicon area is 0.0012 mm2.","PeriodicalId":235336,"journal":{"name":"2014 IEEE 5th Latin American Symposium on Circuits and Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2014-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128376498","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Using FPGAs to implement asynchronous pipelines 使用fpga实现异步管道
2014 IEEE 5th Latin American Symposium on Circuits and Systems Pub Date : 2014-05-26 DOI: 10.1109/LASCAS.2014.6820272
D. L. Oliveira, Kledermon Garcia, R. d'Amore
{"title":"Using FPGAs to implement asynchronous pipelines","authors":"D. L. Oliveira, Kledermon Garcia, R. d'Amore","doi":"10.1109/LASCAS.2014.6820272","DOIUrl":"https://doi.org/10.1109/LASCAS.2014.6820272","url":null,"abstract":"The asynchronous paradigm has interesting features due to the lack of the clock signal and it is another option for the project of digital systems. This paradigm has several design styles, where the micropipeline style is the most suitable one for FPGA platforms, due to the simplicity of its control. In this paper, we propose a pipeline architecture to implement asynchronous digital systems, in bundled-data micropipeline style, considering FPGAs as target devices. Through a case study, we show that the proposed architecture presents a 29% decrease in latency time and a 13% increase in throughput, compared with the state of the art architecture MOUSETRAP.","PeriodicalId":235336,"journal":{"name":"2014 IEEE 5th Latin American Symposium on Circuits and Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2014-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133050869","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
TSVs in early layout design exploration for 3D ICs tsv在3D集成电路早期布局设计探索中的应用
2014 IEEE 5th Latin American Symposium on Circuits and Systems Pub Date : 2014-05-26 DOI: 10.1109/LASCAS.2014.6820323
Mohammad A. Ahmed, M. Chrzanowska-Jeske
{"title":"TSVs in early layout design exploration for 3D ICs","authors":"Mohammad A. Ahmed, M. Chrzanowska-Jeske","doi":"10.1109/LASCAS.2014.6820323","DOIUrl":"https://doi.org/10.1109/LASCAS.2014.6820323","url":null,"abstract":"3D-IC technology discussed in this paper is based on vertical stacking of dies connected by through-silicon-vias (TSV). Vertical stacking helps reducing the wirelength but TSVs occupy space on device layers and their actual positions, arrangement, and physical properties determine the total wirelength. They also introduce thermo-mechanical stress that alters properties of devices that are close to them. Keep-Out-Zone (KOZ) around a single TSV or an island of TSVs is needed to eliminate influence of the thermo-mechanical stress. We use 3D floorplanning tool for early layout design exploration. The KOZ for different shapes and sizes of TSV islands is analyzed and included during floorplanning and TSV impact on wirelength is observed. TSV islands are co-place with circuit blocks to optimize footprint, wirelength and number of TSVs for 3D designs.","PeriodicalId":235336,"journal":{"name":"2014 IEEE 5th Latin American Symposium on Circuits and Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2014-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132073242","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Improving speed and power characteristics of pulse-triggered flip-flops 改进脉冲触发触发器的速度和功率特性
2014 IEEE 5th Latin American Symposium on Circuits and Systems Pub Date : 2014-05-26 DOI: 10.1109/LASCAS.2014.6820287
M. Lanuzza, R. Taco
{"title":"Improving speed and power characteristics of pulse-triggered flip-flops","authors":"M. Lanuzza, R. Taco","doi":"10.1109/LASCAS.2014.6820287","DOIUrl":"https://doi.org/10.1109/LASCAS.2014.6820287","url":null,"abstract":"This paper presents a simple circuital technique to design efficient pulse triggered flip-flops. The proposed approach aims at considerably alleviating the detrimental effects of current contention mechanisms, occurring at critical switching nodes during an output switching. In this way, both latency and power consumption are reduced. The proposed approach is assessed by means of simulations in 90-nm ST commercial CMOS technology. When applied to some recently proposed implicit pulse triggered flip-flop architectures, the suggested design strategy, allows speed to be improved up to 13% and power-delay-product to be lowered down to 14%. Moreover, also the process variation tolerance is considerably improved.","PeriodicalId":235336,"journal":{"name":"2014 IEEE 5th Latin American Symposium on Circuits and Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2014-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123914782","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Specifications for a multi-standard SBCD/ARGOS-3 integrated UHF satellite receiver 多标准SBCD/ARGOS-3集成超高频卫星接收机的规格
2014 IEEE 5th Latin American Symposium on Circuits and Systems Pub Date : 2014-05-26 DOI: 10.1109/LASCAS.2014.6820286
C. C. A. Mendes, G. Cunha, M. Vasilevski, V. Bourguet, S. Catunda, R. N. Lima, M. Barros
{"title":"Specifications for a multi-standard SBCD/ARGOS-3 integrated UHF satellite receiver","authors":"C. C. A. Mendes, G. Cunha, M. Vasilevski, V. Bourguet, S. Catunda, R. N. Lima, M. Barros","doi":"10.1109/LASCAS.2014.6820286","DOIUrl":"https://doi.org/10.1109/LASCAS.2014.6820286","url":null,"abstract":"The specifications for the front-end design of a SBCD/ARGOS-3 integrated UHF receiver in a 0.13 μm star-dard CMOS process are derived. A low intermediate frequency architecture is presented, in which a 3-stage low-noise amplifier, a passive mixer and a phase-locked loop based frequency synthesizer are employed for achieving the resulting specs.","PeriodicalId":235336,"journal":{"name":"2014 IEEE 5th Latin American Symposium on Circuits and Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2014-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116384822","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Design of elliptic curve cryptoprocessors over GF(2163) on Koblitz curves Koblitz曲线上GF(2163)椭圆曲线密码处理器的设计
2014 IEEE 5th Latin American Symposium on Circuits and Systems Pub Date : 2014-05-26 DOI: 10.1109/LASCAS.2014.6820253
Paulo Realpe-Muñoz, V. Trujillo-Olaya, Jaime Velasco-Medina
{"title":"Design of elliptic curve cryptoprocessors over GF(2163) on Koblitz curves","authors":"Paulo Realpe-Muñoz, V. Trujillo-Olaya, Jaime Velasco-Medina","doi":"10.1109/LASCAS.2014.6820253","DOIUrl":"https://doi.org/10.1109/LASCAS.2014.6820253","url":null,"abstract":"This paper presents the design of cryptoprocessors using two multipliers over finite field GF(2163) with digit-level processing. The arithmetic operations were implemented in hardware using Gaussian Normal Bases (GNB) representation and the scalar multiplication kP was performed on Koblitz curves using window-τNAF algorithm with w = 2, 4, 8 and 16. The cryptoprocessors were designed using VHDL description, synthesized on the Stratix-IV FPGA using Quartus II 12.0, and verified using SignalTAP II and Matlab. The simulation results show that the cryptoprocessors present a very good performance using low area. In this case, the computation times for calculating the scalar multiplication for w = 2, 4, 8 and 16 were 9.88, 7.37, 6.17 and 5.05 μs.","PeriodicalId":235336,"journal":{"name":"2014 IEEE 5th Latin American Symposium on Circuits and Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2014-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129713199","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
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