2014 IEEE 5th Latin American Symposium on Circuits and Systems最新文献_第2页

Hardware design of FFT polynomial multipliers FFT多项式乘法器的硬件设计

2014 IEEE 5th Latin American Symposium on Circuits and Systems Pub Date : 2014-05-26 DOI: 10.1109/LASCAS.2014.6820315

Claudia Patricia Renteria-Mejia, A. López-Parrado, Jaime Velasco-Medina

引用次数: 4

Mixed-signal energy feature extractor of EEG frequency bands 脑电频段混合信号能量特征提取器

2014 IEEE 5th Latin American Symposium on Circuits and Systems Pub Date : 2014-05-26 DOI: 10.1109/LASCAS.2014.6820311

Manuel Carrasco-Robles, M. Delgado-Restituto

引用次数: 2

A 6-bit 2GS/s CMOS time-interleaved ADC for analysis of mixed-signal calibration techniques 用于分析混合信号校准技术的6位2GS/s CMOS时间交错ADC

2014 IEEE 5th Latin American Symposium on Circuits and Systems Pub Date : 2014-05-26 DOI: 10.1109/LASCAS.2014.6820267

Benjamín T. Reyes, L. Tealdi, German Paulina, Emanuel Labat, R. Sanchez, P. Mandolesi, M. Hueda

引用次数: 10

New approach to block-level 3D IC layout design 块级3D集成电路版图设计的新方法

2014 IEEE 5th Latin American Symposium on Circuits and Systems Pub Date : 2014-05-26 DOI: 10.1109/LASCAS.2014.6820326

K. Grzesiak-Kopeć, M. Ogorzałek

引用次数: 1

Ginga MiddleWare on a SoC for Digital Television Set-Top Box 数字电视机顶盒SoC上的Ginga中间件

2014 IEEE 5th Latin American Symposium on Circuits and Systems Pub Date : 2014-05-26 DOI: 10.1109/LASCAS.2014.6820290

Bruno Policarpo Toledo Freitas, A. Susin, A. Bonatto

引用次数: 0

Chaotic inductively coupled non-PLL low emission transmitter for implanted devices 用于植入器件的混沌电感耦合非锁相环低发射发射机

2014 IEEE 5th Latin American Symposium on Circuits and Systems Pub Date : 2014-05-26 DOI: 10.1109/LASCAS.2014.6820295

Ruchir Saraswat, E. Rodríguez-Villegas

引用次数: 0

Predictive DTC algorithm for induction machines using Sliding Horizon Prediction 基于滑动水平预测的感应电机预测直接转矩控制算法

2014 IEEE 5th Latin American Symposium on Circuits and Systems Pub Date : 2014-05-26 DOI: 10.1109/LASCAS.2014.6820265

J. Rengifo, J. Aller, A. Berzoy, J. Restrepo

引用次数: 9

SICARELO: A tool for synthesis of locally-clocked extended burst-mode asynchronous Controllers SICARELO:一个用于合成本地时钟扩展突发模式异步控制器的工具

2014 IEEE 5th Latin American Symposium on Circuits and Systems Pub Date : 2014-05-26 DOI: 10.1109/LASCAS.2014.6820270

T. Curtinhas, D. L. Oliveira, D. Bompean, L. Faria, L. Romano

{"title":"SICARELO: A tool for synthesis of locally-clocked extended burst-mode asynchronous Controllers","authors":"T. Curtinhas, D. L. Oliveira, D. Bompean, L. Faria, L. Romano","doi":"10.1109/LASCAS.2014.6820270","DOIUrl":"https://doi.org/10.1109/LASCAS.2014.6820270","url":null,"abstract":"Controllers based on Synchronous Finite State Machines (SFSM) are widely used in the control unit design of complex digital systems. These systems can present critical requirements, such as power consumption, robustness, speed, etc. In this context, the asynchronous paradigm shows interesting features that fit as an alternative for the design, but the lack of appropriate tools and the high difficulty of the design are already drawbacks. This paper proposes a new tool called SICARELO to automatic synthesis of asynchronous FSMs with local clock. The existence of a local clock reduces the requirements of asynchronous logic, enabling the synthesis in any PLD, such as CPLDs and FPGAs, without the need of satisfying any type of macro-cells mapping. The proposed tool starts from a popular specification known as Extended Burst Mode (XBM). The tool SICARELO was tested on a set of benchmarks, compared with 3D and Minimalist tools that are state of the art. SICARELO tool obtained a reduction media in the combinatorial logic of 32% of products and 25% of literals in the XBM_AFSM synthesis with local clock.","PeriodicalId":235336,"journal":{"name":"2014 IEEE 5th Latin American Symposium on Circuits and Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2014-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133317006","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11

Piezoresistive cantilever platform for label-free detection of molecules 用于无标签分子检测的压阻悬臂平台

2014 IEEE 5th Latin American Symposium on Circuits and Systems Pub Date : 2014-05-26 DOI: 10.1109/LASCAS.2014.6820319

Bahareh Gholamzadeh, E. Ghafar-Zadeh, F. Awwad, M. Sawan

{"title":"Piezoresistive cantilever platform for label-free detection of molecules","authors":"Bahareh Gholamzadeh, E. Ghafar-Zadeh, F. Awwad, M. Sawan","doi":"10.1109/LASCAS.2014.6820319","DOIUrl":"https://doi.org/10.1109/LASCAS.2014.6820319","url":null,"abstract":"MEMS sensors can be used for label-free detection in many different biological studies. Usually in this procedure the presence of special substance in a sample can be monitored based on its interaction and binding with specific probe molecules which are immobilized on a sensor. These interactions will result into variations which can be detected by biosensors. Developing a low cost, high throughput system for performing label-free detection can be beneficial for different studies. This type of platform can be used for real-time detection of multiple molecules with high sensitivity. As a first step towards developing such platform, in this paper we present a label-free detection system using an array of 30 cantilevers implemented through standard MEMS foundry process (MetalMUMPs). Herein, we discuss the design, fabrication, and characterization results of the proposed platform using electrical and interferometry techniques. The results from simulations have shown that sensors can be used for measuring small forces in range of nN and pN and the characterization tests have proven that sensors are functional and they are ready to be used in biological experiments.","PeriodicalId":235336,"journal":{"name":"2014 IEEE 5th Latin American Symposium on Circuits and Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2014-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134376069","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Exploring pel decimation to trade off between energy and quality in video coding 探索在视频编码中实现能量和质量平衡的像素抽取方法

2014 IEEE 5th Latin American Symposium on Circuits and Systems Pub Date : 2014-05-26 DOI: 10.1109/LASCAS.2014.6820316

Ismael Seidel, André Beims Bräscher, M. Monteiro, Jose Luis Giintzel

{"title":"Exploring pel decimation to trade off between energy and quality in video coding","authors":"Ismael Seidel, André Beims Bräscher, M. Monteiro, Jose Luis Giintzel","doi":"10.1109/LASCAS.2014.6820316","DOIUrl":"https://doi.org/10.1109/LASCAS.2014.6820316","url":null,"abstract":"This work investigates the trade-offs between energy and quality in video coding when pel decimation is applied. Realistic estimates for area and energy per block were obtained by simulating five different architectures specially designed to compute the Sum of Absolute Differences (SAD) for 4×4 pixel blocks. Among these architectures, one can be configured to operate with 1:1, 4:3, 2:1 or 4:1 sample ratios, whereas the rest are tailored to operate exclusively with each one of those ratios. The five VLSI architectures were logically synthesized for a 45 nm industrial standard cell library for a target frequency and also for the maximum achievable frequency. They were also simulated with 100 k input vectors obtained by using an H.264/AVC encoder running on one full HD (1080p) video sample. The obtained results show that by using the configurable architecture with full sampling, the best energy/block result was 3.54 pJ/block (60% better than the non-configurable with 7.08 pJ/block). The energy/block value can be further reduced until 1.34 pJ/block at the cost of 2.8% in PSNR, on average, and 14.1% in SSIM, on average.","PeriodicalId":235336,"journal":{"name":"2014 IEEE 5th Latin American Symposium on Circuits and Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2014-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123738933","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7