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2014 IEEE 5th Latin American Symposium on Circuits and Systems最新文献

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A low power biopotential amplifier in 0.35um CMOS for portable EEG signal amplification 一种用于便携式脑电图信号放大的0.35um CMOS低功耗生物电位放大器
2014 IEEE 5th Latin American Symposium on Circuits and Systems Pub Date : 2014-02-01 DOI: 10.1109/LASCAS.2014.6820282
Yong Hooi Lim, Likun Xia
{"title":"A low power biopotential amplifier in 0.35um CMOS for portable EEG signal amplification","authors":"Yong Hooi Lim, Likun Xia","doi":"10.1109/LASCAS.2014.6820282","DOIUrl":"https://doi.org/10.1109/LASCAS.2014.6820282","url":null,"abstract":"In this paper, a low power differential biopotential amplifier (BPA) targeted for front-end electroencephalogram (EEG) signal amplification is reported. The proposed BPA is chopper stabilized to minimize flicker noise or 1/f noise, improving the fidelity of the signal measurement. This work aims to provide a low power BPA design solution for portable EEG application. This work proposes a non-overlapping clocking scheme for demodulation chopping for chopping artifacts reduction while maintaining low power consumption. This work is simulated in MIMOS 0.35um CMOS process and has achieved around 57dB of gain, ultra-low power consumption of 0.81μW with noise performance of 347nV/sqrt(Hz) and supply voltage of 1.8V.","PeriodicalId":235336,"journal":{"name":"2014 IEEE 5th Latin American Symposium on Circuits and Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2014-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123921572","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Reconfigurable hardware architecture for music generation using cellular automata 使用元胞自动机生成音乐的可重构硬件架构
2014 IEEE 5th Latin American Symposium on Circuits and Systems Pub Date : 2014-02-01 DOI: 10.1109/LASCAS.2014.6820309
Heloisa Dina Bezerra, N. Nedjah, L. M. Mourelle
{"title":"Reconfigurable hardware architecture for music generation using cellular automata","authors":"Heloisa Dina Bezerra, N. Nedjah, L. M. Mourelle","doi":"10.1109/LASCAS.2014.6820309","DOIUrl":"https://doi.org/10.1109/LASCAS.2014.6820309","url":null,"abstract":"This paper proposes a hardware architecture to generate harmonized music, which is composed by melodic intervals determined from the association of cellular automata in accordance to standard MIDI protocol. The implementation of the architecture is implemented in FPGA aiming at designing an alternative efficient tool for the study and research related to the field of random music. To this end, the architecture includes four kind of cellular automata, developed through four neighborhood models with a radius of 1. The proposed architecture allows 16 possible combinations of cellular automata models. to maximize the applicability potential of the architecture, the configuration data that influence the generated music product is performed almost in entirety by the user, with no virtual limit of the number of possible melodic combinations generated by the hardware. In order to validate the effectiveness as well as efficiency of the architecture, we present some results about the generated melodies. The results were extracted by means of known musical information retrieval techniques.","PeriodicalId":235336,"journal":{"name":"2014 IEEE 5th Latin American Symposium on Circuits and Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2014-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124571392","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Automatic layout synthesis with ASTRAN applied to asynchronous cells 自动布局合成与ASTRAN应用于异步细胞
2014 IEEE 5th Latin American Symposium on Circuits and Systems Pub Date : 2014-02-01 DOI: 10.1109/LASCAS.2014.6820314
A. Ziesemer, R. Reis, Matheus T. Moreira, Michel Evandro Arendt, Ney Laert Vilar Calazans
{"title":"Automatic layout synthesis with ASTRAN applied to asynchronous cells","authors":"A. Ziesemer, R. Reis, Matheus T. Moreira, Michel Evandro Arendt, Ney Laert Vilar Calazans","doi":"10.1109/LASCAS.2014.6820314","DOIUrl":"https://doi.org/10.1109/LASCAS.2014.6820314","url":null,"abstract":"This work presents ASTRAN, a tool for automatic layout generation of cell libraries, and the use of this tool in the production of a cell library for asynchronous logic components called ASCEnD. In this context, ASTRAN is able to achieve orders of magnitude savings in cell generation time if compared to manual design. ASTRAN supports technologies down to 65nm and simultaneous two-dimensional cell layout compaction. It can deal with non-complementary logic cells, and allows producing any type of transistor network. The comparison of the generated layouts to those of the hand designed ASCEnD library revealed that ASTRAN achieves an average of 26% less area, about 50% less total parasitic capacitance and worst case input capacitance, and 23% lower delay.","PeriodicalId":235336,"journal":{"name":"2014 IEEE 5th Latin American Symposium on Circuits and Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2014-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131032304","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
Derivation of fractional order differentiators 分数阶微分的推导
2014 IEEE 5th Latin American Symposium on Circuits and Systems Pub Date : 1900-01-01 DOI: 10.1109/LASCAS.2014.6820306
M. Hasan
{"title":"Derivation of fractional order differentiators","authors":"M. Hasan","doi":"10.1109/LASCAS.2014.6820306","DOIUrl":"https://doi.org/10.1109/LASCAS.2014.6820306","url":null,"abstract":"Fractional order differentiator has been applied successfully to fractional order PID controller, signal processing, and image processing. In this paper IIR fractional differentiators are developed. Specifically, fractional delay filters in rational form are used to approximate fractional differentiators by incorporating square root Pade approximants with Simpson's and Boole's' differential operators.","PeriodicalId":235336,"journal":{"name":"2014 IEEE 5th Latin American Symposium on Circuits and Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128881076","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Throughput driven check point selection in suspicious timing error prediction based designs 基于可疑时序误差预测设计的吞吐量驱动检查点选择
2014 IEEE 5th Latin American Symposium on Circuits and Systems Pub Date : 1900-01-01 DOI: 10.1109/LASCAS.2014.6820280
Hiroaki Igarashi, Youhua Shi, M. Yanagisawa, N. Togawa
{"title":"Throughput driven check point selection in suspicious timing error prediction based designs","authors":"Hiroaki Igarashi, Youhua Shi, M. Yanagisawa, N. Togawa","doi":"10.1109/LASCAS.2014.6820280","DOIUrl":"https://doi.org/10.1109/LASCAS.2014.6820280","url":null,"abstract":"In this paper, a throughput-driven design technique is proposed, in which a suspicious timing error prediction circuit is inserted to monitor the signal transitions at some selected check points. Unlike previous works where timing errors are detected after their occurrence, the proposed method tries to use the real intermediate signal transitions for timing error prediction. The check point selection will affect both the maximal operation frequency and the suspicious timing error overestimation rate, both of which have an effect on the overall throughput, thus an analysis on the check point selection is also given. In our work, the circuit can be overclocked by a factor of 2 or more with ignorable area overhead while guarantees the always-correct output.","PeriodicalId":235336,"journal":{"name":"2014 IEEE 5th Latin American Symposium on Circuits and Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123274514","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Methods for fractional delay approximation 分数阶延迟近似的方法
2014 IEEE 5th Latin American Symposium on Circuits and Systems Pub Date : 1900-01-01 DOI: 10.1109/LASCAS.2014.6820307
M. Hasan
{"title":"Methods for fractional delay approximation","authors":"M. Hasan","doi":"10.1109/LASCAS.2014.6820307","DOIUrl":"https://doi.org/10.1109/LASCAS.2014.6820307","url":null,"abstract":"Fractional delay filters have been common devices in many digital systems. They are used for implementing discrete-time systems which include delays that are not multiples of the sampling period. In this paper ideal fractional delay transfer function is approximated using some generalization of Taylor expansion known as Hummel-Seebeck-Obreshkov (HSO) expansion. When HSO is applied to fractional delay it leads to rational approximation that is equivalent to Pade approximation. Numerical results show that the proposed approximations are efficient.","PeriodicalId":235336,"journal":{"name":"2014 IEEE 5th Latin American Symposium on Circuits and Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113999313","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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