Automatic layout synthesis with ASTRAN applied to asynchronous cells

Abstract

This work presents ASTRAN, a tool for automatic layout generation of cell libraries, and the use of this tool in the production of a cell library for asynchronous logic components called ASCEnD. In this context, ASTRAN is able to achieve orders of magnitude savings in cell generation time if compared to manual design. ASTRAN supports technologies down to 65nm and simultaneous two-dimensional cell layout compaction. It can deal with non-complementary logic cells, and allows producing any type of transistor network. The comparison of the generated layouts to those of the hand designed ASCEnD library revealed that ASTRAN achieves an average of 26% less area, about 50% less total parasitic capacitance and worst case input capacitance, and 23% lower delay.