Claudia Patricia Renteria-Mejia, A. López-Parrado, Jaime Velasco-Medina
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引用次数: 4
摘要
本文介绍了两个FFT多项式乘法器的并行和顺序结构设计。并行多项式乘法器和顺序多项式乘法器分别针对吞吐量和面积资源进行了优化。设计用通用结构VHDL描述，在Stratix EP4SGX230KF40C2上使用Quartus II V. 13进行合成，并使用SignalTap进行验证。硬件综合和性能结果表明，所设计的乘法器具有良好的面积-吞吐量权衡，适用于高性能科学计算应用。
This paper presents the design of two FFT polynomial multipliers using parallel and sequential architectures. Parallel and sequential polynomial multipliers were optimized for throughput and area resources, respectively. The designs are described in generic structural VHDL, synthesized on the Stratix EP4SGX230KF40C2 using Quartus II V. 13, and verified using SignalTap. The hardware synthesis and performance results show that the designed multipliers present a good area-throughput trade-off and they are suitable for high-performance scientific computing applications.
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