13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05)最新文献_第4页

Higher radix floating-point representations for FPGA-based arithmetic 基于fpga算法的高基数浮点表示

13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05) Pub Date : 2005-04-18 DOI: 10.1109/FCCM.2005.43

Bryan Catanzaro, B. Nelson

{"title":"Higher radix floating-point representations for FPGA-based arithmetic","authors":"Bryan Catanzaro, B. Nelson","doi":"10.1109/FCCM.2005.43","DOIUrl":"https://doi.org/10.1109/FCCM.2005.43","url":null,"abstract":"FPGA implementations of floating-point operators have historically been designed to use binary floating-point representations. The general computing world settled on binary floating-point representations over three decades ago, and more recently, the FPGA community followed their example. Binary representations were chosen to maximize numerical accuracy per bit of data, however, the unique nature of FPGA-based computation makes numerical accuracy per unit of FPGA resources a more important measure of the usefulness of a given floating-point representation. In this paper, we show that higher radix floating-point representations are well suited to FPGA-based computations, especially high precision calculations which require the support of denormalized numbers. Higher radix representations use FPGA resources more efficiently. For example, a hexadecimal floating-point adder has a 30% smaller area-time product than its binary counterpart, while still delivering equal worst-case and better average-case numerical accuracy. Contrary to established belief, higher radix representations are useful for FPGA applications requiring IEEE 754 compliance, since they can deliver superior numerical performance while still using less FPGA resources.","PeriodicalId":222425,"journal":{"name":"13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114164042","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 35

An architecture for video compression based on the SCAN algorithm 基于SCAN算法的视频压缩体系结构

13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05) Pub Date : 2005-04-18 DOI: 10.1109/FCCM.2005.17

H. Sofikitis, K. Roumpou, A. Dollas, N. Bourbakis

引用次数: 5

Reconfigurable designs for radiosity 可重构的辐射设计

13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05) Pub Date : 2005-04-18 DOI: 10.1109/FCCM.2005.57

P. Baker, T. Todman, Henry Styles, W. Luk

引用次数: 6

The Erlangen Slot Machine: a highly flexible FPGA-based reconfigurable platform Erlangen老虎机:一个高度灵活的基于fpga的可重构平台

13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05) Pub Date : 2005-04-18 DOI: 10.1109/FCCM.2005.63

C. Bobda, Mateusz Majer, A. Ahmadinia, T. Haller, A. Linarth, J. Teich, S. Fekete, J. V. D. Veen

引用次数: 52

Modeling and FPGA implementation of applications using parameterized process networks with non-static parameters 使用非静态参数的参数化过程网络的建模和FPGA实现

13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05) Pub Date : 2005-04-18 DOI: 10.1109/FCCM.2005.47

Hristo Nikolov, T. Stefanov, E. Deprettere

引用次数: 17

Hardware solution to Java compressed heap Java压缩堆的硬件解决方案

13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05) Pub Date : 2005-04-18 DOI: 10.1109/FCCM.2005.41

Mayumi Kato, D. Lo

引用次数: 2

Hardware factorization based on elliptic curve method 基于椭圆曲线方法的硬件分解

13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05) Pub Date : 2005-04-18 DOI: 10.1109/FCCM.2005.40

M. Simka, J. Pelzl, T. Kleinjung, J. Franke, C. Priplata, C. Stahlke, M. Drutarovský, V. Fischer

{"title":"Hardware factorization based on elliptic curve method","authors":"M. Simka, J. Pelzl, T. Kleinjung, J. Franke, C. Priplata, C. Stahlke, M. Drutarovský, V. Fischer","doi":"10.1109/FCCM.2005.40","DOIUrl":"https://doi.org/10.1109/FCCM.2005.40","url":null,"abstract":"The security of the most popular asymmetric cryptographic scheme RSA depends on the hardness of factoring large numbers. The best known method for factorization large integers is the general number field sieve (GNFS). Recently, architectures for special purpose hardware for the GNFS have been proposed. One important step within the GNFS is the factorization of mid-size numbers for smoothness testing, an efficient algorithm for which is the elliptic curve method (ECM). Since the smoothness testing is also suitable for parallelization, it is promising to improve ECM via special-purpose hardware. We show that massive parallel and cost efficient ECM hardware engines can improve the cost-time product of the RSA moduli factorization via the GNFS considerably. The computation of ECM is a classical example for an algorithm that can be significantly accelerated through special-purpose hardware. In this work, we present an efficient hardware implementation of ECM to factor numbers up to 200 bits, which is also scalable to other bit lengths. For proof-of-concept purposes, ECM is realized as a software-hardware co-design on an FPGA and an embedded microcontroller. This appears to be the first publication of a realized hardware implementation of ECM, and the first description of GNFS acceleration through hardware-based ECM.","PeriodicalId":222425,"journal":{"name":"13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129148330","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 26

Massively parallel processors generator for reconfigurable system 用于可重构系统的大规模并行处理器生成器

13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05) Pub Date : 2005-04-18 DOI: 10.1109/FCCM.2005.45

T. Hamada, N. Nakasato

引用次数: 12

Core-based methodology: an automated approach for implementing a complete system from algorithms to a heterogeneous network including FPGAs 基于核心的方法:一种实现完整系统的自动化方法，从算法到包括fpga在内的异构网络

13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05) Pub Date : 2005-04-18 DOI: 10.1109/FCCM.2005.29

J. Lam, J. McAllister, J. Dudley

引用次数: 0

Performance and cost analysis of time-multiplexed execution on the dynamically reconfigurable processor 动态可重构处理器上时间复用执行的性能与成本分析

13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05) Pub Date : 2005-04-18 DOI: 10.1109/FCCM.2005.52

H. Amano, Shohei Abe, Y. Hasegawa, Katsuaki Deguchi, Masayasu Suzuki

引用次数: 18