13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05)最新文献

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Efficient hardware data mining with the Apriori algorithm on FPGAs 基于fpga的Apriori算法的高效硬件数据挖掘
Z. Baker, V. Prasanna
{"title":"Efficient hardware data mining with the Apriori algorithm on FPGAs","authors":"Z. Baker, V. Prasanna","doi":"10.1109/FCCM.2005.31","DOIUrl":"https://doi.org/10.1109/FCCM.2005.31","url":null,"abstract":"The Apriori algorithm is a popular correlation-based data mining kernel. However, it is a computationally expensive algorithm and the running times can stretch up to days for large databases, as database sizes can extend to Gigabytes. Through the use of a new extension to the systolic array architecture, time required for processing can be significantly reduced. Our array architecture implementation on a Xilinx Virtex-II Pro 100 provides a performance improvement that can be orders of magnitude faster than the state-of-the-art software implementations. The system is easily scalable and introduces an efficient \"systolic injection\" method for intelligently reporting unpredictably generated mid-array results to a controller without any chance of collision or excessive stalling.","PeriodicalId":222425,"journal":{"name":"13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05)","volume":"125 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129325807","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 104
Automating the layout of reconfigurable subsystems using circuit generators 使用电路发生器实现可重构子系统的自动化布局
Shawn Phillips, S. Hauck
{"title":"Automating the layout of reconfigurable subsystems using circuit generators","authors":"Shawn Phillips, S. Hauck","doi":"10.1109/FCCM.2005.24","DOIUrl":"https://doi.org/10.1109/FCCM.2005.24","url":null,"abstract":"When designing systems-on-a-chip (SoCs), a unique opportunity exists to generate custom FPGA architectures that are specific to the application domain in which the device is used. The inclusion of such devices provides an efficient compromise between the flexibility of software and the performance of hardware, while at the same time allowing for post-fabrication modification of the SoC. To automate the layout of reconfigurable subsystems for systems-on-a-chip, we present the circuit generator method. The circuit generator method enables a designer to leverage the regularity that exists in FPGAs, creating structures that have only the needed resources to support the specified application domain. To facilitate this we have created generators that automatically produce the various components of the custom reconfigurable device. Compared to the unaltered full-custom tile, we achieve designs that are on average approximately 46% smaller and 16% faster, while continuing to support the algorithms in the particular application domain.","PeriodicalId":222425,"journal":{"name":"13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131002426","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
On distributed reconfigurable systems: open problems and some initial solutions 分布式可重构系统:开放性问题和一些初步解决方案
A. Dollas, D. Efstathiou, G. Vernardos, Elias Polytarchos, Konstantinos Kazakos
{"title":"On distributed reconfigurable systems: open problems and some initial solutions","authors":"A. Dollas, D. Efstathiou, G. Vernardos, Elias Polytarchos, Konstantinos Kazakos","doi":"10.1109/FCCM.2005.49","DOIUrl":"https://doi.org/10.1109/FCCM.2005.49","url":null,"abstract":"By \"distributed reconfigurable systems\" we mean systems of distributed resources, which include dynamically reconfigurable FPGA components. There already exist systems such as wearable computers with distributed reconfigurable resources, but the broader area is rather unexplored. Reconfigurable distributed systems have some unique characteristics or desired behavior, which merit further study. To illustrate, any attempt for a full implementation of TCP/IP in hardware leads to prohibitively expensive solutions for low-cost sensor networks. Therefore, lighter protocols are needed. However, whereas data exchange can be effectively done through unreliable communication channels, reconfiguration assumes that a reliable data stream has to be provided for purposes of reconfiguration. Whereas a bit error rate (BER) due to noise, etc. can pose no problem in data communication, it would effectively lead to inability to reconfigure just about any present day reconfigurable device, unless accounted for at the protocol level. And yet we just dismissed TCP/IP as a protocol, although it would have provided for the desired robustness.","PeriodicalId":222425,"journal":{"name":"13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05)","volume":"170 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114454868","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Fast reconfiguring deep packet filter for 1+ gigabit network 快速重新配置深度包过滤1+千兆网络
Young H. Cho, W. Mangione-Smith
{"title":"Fast reconfiguring deep packet filter for 1+ gigabit network","authors":"Young H. Cho, W. Mangione-Smith","doi":"10.1109/FCCM.2005.34","DOIUrl":"https://doi.org/10.1109/FCCM.2005.34","url":null,"abstract":"Due to increasing number of network worms and virus, many computer network users are vulnerable to attacks. Unless network security systems use more advanced methods of content filtering such as deep packet inspection, the problem get worse. However, searching for patterns at multiple offsets in entire content of network packet requires more processing power than most general purpose processor can provide. Thus, researchers have developed high performance parallel deep packet filters for reconfigurable devices. Although some reconfigurable systems can be generated automatically from pattern database, obtaining high performance result from each subsequent reconfiguration can be a time consuming process. We present a novel architecture for programmable parallel pattern matching coprocessor. By combining a scalable coprocessor with the compact reconfigurable filter, we produce a hybrid system that is able to update the rules immediate during the time the new filter is being compiled. We mapped our hybrid filter for the latest Snort rule set on January 13, 2005, containing 2,044 unique patterns byte make up 32,384 bytes, onto a single Xilinx Virtex 4LX-XC4VLX15 FPGA with a filtering rate of 2 Gbps.","PeriodicalId":222425,"journal":{"name":"13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121024365","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 66
Prototyping architectural support for program rollback using FPGAs 使用fpga的程序回滚的原型架构支持
R. Teodorescu, J. Torrellas
{"title":"Prototyping architectural support for program rollback using FPGAs","authors":"R. Teodorescu, J. Torrellas","doi":"10.1109/FCCM.2005.55","DOIUrl":"https://doi.org/10.1109/FCCM.2005.55","url":null,"abstract":"This paper presents a processor and memory-hierarchy prototype based on FPGAs that provides hardware support for program rollback. We use this prototype to demonstrate how compiler- or user-controlled speculative execution can help in debugging production codes. The system is based on a synthesizable VHDL implementation of a 32-bit processor compliant with the SPARC V8 architecture. We conduct experiments on applications with real bugs. The applications run on top of a version of Linux ported to this hardware. Our experiments show that our system is able to successfully execute the buggy code sections speculatively. This allows the thorough characterization of the faulty code through repeated rollback and re-execution. Moreover, the hardware extensions we made to the baseline system increase the hardware resource requirements by less than 4.5%.","PeriodicalId":222425,"journal":{"name":"13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05)","volume":"158 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124346802","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
Handling different computational granularity by a reconfigurable IC featuring embedded FPGAs and a network-on-chip 通过嵌入式fpga和片上网络的可重构集成电路处理不同的计算粒度
F. Lertora, M. Borgatti
{"title":"Handling different computational granularity by a reconfigurable IC featuring embedded FPGAs and a network-on-chip","authors":"F. Lertora, M. Borgatti","doi":"10.1109/FCCM.2005.39","DOIUrl":"https://doi.org/10.1109/FCCM.2005.39","url":null,"abstract":"A system-on-chip integrating a microprocessor, three embedded FPGA (eFPGA) and an eight port network-on-chip (NoC) is implemented in a 90nm CMOS technology. The system has been designed to execute complex multimedia applications by the use of hardware accelerators mapped to a reconfigurable platform based on a message-passing architecture. Computational kernels are mapped as hardware autonomous processes inside the eFPGAs or locally accelerated by the usage of dedicated microprocessor coprocessors. Each eFPGA on the system can be independently programmed and share logic with the others eFPGAs by intra-communication channels. The architecture is highly scalable since the eFPGA number can be controlled and the reconfigurable platform communication channels are based on a configurable NoC. The silicon area required by the system is 26mm2 in a 90 nm CMOS process. 10x speed ups have been measured on a MP3 playler mapping example.","PeriodicalId":222425,"journal":{"name":"13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129864564","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A framework for rule processing in reconfigurable network systems 可重构网络系统中规则处理的框架
Michael Attig, J. Lockwood
{"title":"A framework for rule processing in reconfigurable network systems","authors":"Michael Attig, J. Lockwood","doi":"10.1145/1046192.1046259","DOIUrl":"https://doi.org/10.1145/1046192.1046259","url":null,"abstract":"High-performance rule processing systems are needed by network administrators in order to protect Internet systems from attack. Researchers have been working to implement components of intrusion detection systems (IDS), such as the highly popular Snort system, in reconfigurable hardware. While considerable progress has been made in the areas of string matching and header processing, complete systems have not yet been demonstrated that effectively combine all of the functionality necessary to perform rule processing for network systems. In this paper, a framework for implementing a rule processing system in reconfigurable hardware is presented. The framework integrates the functionality to scan dataflows for regular expressions, fixed strings, and header values. It also allows modules to be added to perform extended functionality to support all features found in Snort rules. Reconfigurability and flexibility are key components of the framework that enable it to adapt to protect Internet systems from threats including malicious worms, computer viruses, and network intruders. To prove the framework viable, a system has been built that scans all bytes of transmission control protocol/Internet protocol (TCP/IP) traffic entering and leaving a network's gateway at multi-gigabit rates. Using Xilinx FPGA hardware on the field programmable port extender (FPX) platform, the framework can process 32,768 complex rules at data rates of 2.5 Gbps. Systems to handle data at 10 Gbps rates can be built today using the same framework in the latest reconfigurable hardware devices such as the Virtex 4.","PeriodicalId":222425,"journal":{"name":"13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121155466","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 41
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