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13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05)最新文献

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A general purpose, highly efficient communication controller architecture for hardware acceleration platforms 用于硬件加速平台的通用、高效的通信控制器体系结构
13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05) Pub Date : 2005-04-18 DOI: 10.1109/FCCM.2005.8
P. Curt, J. Durbano, F. Ortiz, J. Humphrey, D. Prather
{"title":"A general purpose, highly efficient communication controller architecture for hardware acceleration platforms","authors":"P. Curt, J. Durbano, F. Ortiz, J. Humphrey, D. Prather","doi":"10.1109/FCCM.2005.8","DOIUrl":"https://doi.org/10.1109/FCCM.2005.8","url":null,"abstract":"Although researchers have presented individual techniques to efficiently utilize the peripheral component interconnect (PCI) bus, their contributions fail to provide a direct path to large communication bandwidth for FPGA-based hardware accelerators. Because of the increasing use of FPGAs as application accelerators, there is a need for another, more powerful communication layer to sustain very large data transfers. This paper presents the implementation of such an infrastructure and provides the designer with a familiar, easy-to-use interface. When incorporated into existing designs, 30-fold speed improvements over off-the-shelf PCI cores from Xilinx have been demonstrated.","PeriodicalId":222425,"journal":{"name":"13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114978839","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Caronte: a complete methodology for the implementation of partially dynamically self-reconfiguring systems on FPGA platforms 在FPGA平台上实现部分动态自重新配置系统的完整方法
13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05) Pub Date : 2005-04-18 DOI: 10.1109/FCCM.2005.25
A. Donato, Fabrizio Ferrandi, M. Redaelli, M. Santambrogio, D. Sciuto
{"title":"Caronte: a complete methodology for the implementation of partially dynamically self-reconfiguring systems on FPGA platforms","authors":"A. Donato, Fabrizio Ferrandi, M. Redaelli, M. Santambrogio, D. Sciuto","doi":"10.1109/FCCM.2005.25","DOIUrl":"https://doi.org/10.1109/FCCM.2005.25","url":null,"abstract":"It is common nowadays to employ FPGAS, not only as a means of rapidly prototyping and testing dedicated solutions, but also as a platform on which to implement actual production systems. Although modern FPGAS allow the designer to modify dynamically even only portions of the chip, to this date there is a lack of satisfying design methodologies that using only non-proprietary widely available tools make it possible to optimally implement a high-level specification into a partially dynamically reconfigurable system. The aim of this work is to propose a methodology for solving this problem. The main features of the Caronte methodology are: 1. full exploitation of partial dynamic reconfiguration; 2. the reconfiguration is internal; 3. a real-time Unix-like operating system helps the management of complex systems with multiple tasks, and simplifies reconfiguration through an optimized device driver.","PeriodicalId":222425,"journal":{"name":"13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126172083","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
FPGA-based CDMA switch for networks-on-chip 基于fpga的片上网络CDMA开关
13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05) Pub Date : 2005-04-18 DOI: 10.1109/FCCM.2005.37
Daewook Kim, Manho Kim, G. Sobelman
{"title":"FPGA-based CDMA switch for networks-on-chip","authors":"Daewook Kim, Manho Kim, G. Sobelman","doi":"10.1109/FCCM.2005.37","DOIUrl":"https://doi.org/10.1109/FCCM.2005.37","url":null,"abstract":"This paper presents timing and area results for an FPGA implementation of a CDMA-based switch for networks-on-chip. The design was mapped onto the Xilinx Virtex4 XC4VLX200 device using Synplify Pro for a range of pay-load sizes. The synthesis results give the area and maximum frequency obtained. Simulation verifies the desired functionality and provides throughput and latency values as functions of payload size.","PeriodicalId":222425,"journal":{"name":"13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05)","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126646693","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Exploiting multi-grained parallelism in reconfigurable SBC architectures 在可重构的SBC体系结构中利用多粒度并行性
13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05) Pub Date : 2005-04-18 DOI: 10.1109/FCCM.2005.33
Joseph Zambreno, Daniel Honbo, A. Choudhary
{"title":"Exploiting multi-grained parallelism in reconfigurable SBC architectures","authors":"Joseph Zambreno, Daniel Honbo, A. Choudhary","doi":"10.1109/FCCM.2005.33","DOIUrl":"https://doi.org/10.1109/FCCM.2005.33","url":null,"abstract":"In recent years, reconfigurable technology has emerged as a popular choice for implementing various types of cryptographic functions. Nevertheless, an insufficient amount effort has been placed into fully exploiting the tremendous amounts of parallelism intrinsic to FPGAs for this class of algorithms. In this paper, we focus on block cipher architectures and explore design decisions that leverage the multi-grained parallelism inherent in many of these algorithms. We demonstrate the usefulness of this approach with a highly parallel FPGA implementation of the AES standard and present results detailing the area/delay tradeoffs resulting from our design decisions.","PeriodicalId":222425,"journal":{"name":"13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123638317","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Accelerating applications by mapping critical kernels on coarse-grain reconfigurable hardware in hybrid systems 通过在混合系统中粗粒度可重构硬件上映射关键核来加速应用
13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05) Pub Date : 2005-04-18 DOI: 10.1109/FCCM.2005.15
M. D. Galanis, G. Dimitroulakos, C. Goutis
{"title":"Accelerating applications by mapping critical kernels on coarse-grain reconfigurable hardware in hybrid systems","authors":"M. D. Galanis, G. Dimitroulakos, C. Goutis","doi":"10.1109/FCCM.2005.15","DOIUrl":"https://doi.org/10.1109/FCCM.2005.15","url":null,"abstract":"In this paper, we propose a method for speeding-up applications by partitioning them between the reconfigurable hardware blocks of different granularity and mapping critical parts of applications on the coarse-grain reconfigurable hardware. The partitioning method consists of four steps; the intermediate representation creation, the kernel identification, the mapping onto coarse-grain reconfigurable blocks, and the mapping onto the FPGA hardware. The method is validated using five real-world applications, where the speedup relative to an all-FPGA solution ranges from 1.4 to 3.1.","PeriodicalId":222425,"journal":{"name":"13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132194341","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Astrophysical hydrodynamics simulations on a reconfigurable system 可重构系统的天体物理流体动力学模拟
13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05) Pub Date : 2005-04-18 DOI: 10.1109/FCCM.2005.21
N. Nakasato, T. Hamada
{"title":"Astrophysical hydrodynamics simulations on a reconfigurable system","authors":"N. Nakasato, T. Hamada","doi":"10.1109/FCCM.2005.21","DOIUrl":"https://doi.org/10.1109/FCCM.2005.21","url":null,"abstract":"The smoothed particle hydrodynamics (SPH) method is a widely used particle simulation scheme in astrophysical hydrodynamics simulations. Since a possible problem size of SPH simulations is limited by available computational resource, it is natural to implement a computation intensive core of the SPH simulations on a FPGA based reconfigurable board. We are now implementing SPH simulations on our FPGA based board PROGRAPE-3. Using our developed software, implementation of the SPH simulation becomes quite straightforward. Our \"SPH processors\", which compute particle interaction force by reduced accuracy floating-point operations, run at 66 MHz on our board. Obtained real performance of the SPH processors is 38 Gflops. Our results indicate using FPGA chips for floating-point intensive astrophysical simulations is being feasible.","PeriodicalId":222425,"journal":{"name":"13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132465133","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
Interleaving behavioral and cycle-accurate descriptions for reconfigurable hardware compilation 可重构硬件编译的交错行为和周期精确描述
13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05) Pub Date : 2005-04-18 DOI: 10.1109/FCCM.2005.44
J. Coutinho, Jun Jiang, W. Luk
{"title":"Interleaving behavioral and cycle-accurate descriptions for reconfigurable hardware compilation","authors":"J. Coutinho, Jun Jiang, W. Luk","doi":"10.1109/FCCM.2005.44","DOIUrl":"https://doi.org/10.1109/FCCM.2005.44","url":null,"abstract":"This paper describes Haydn, a hardware compilation approach which aims to combine the benefits of cycle accurate descriptions such as ease of control and performance, and the rapid development and design exploration facilities in behavioral synthesis tools. Our approach supports two main features: deriving architectures that meet performance goals involving metrics such as resource usage and execution time, and inferring design behavior by generating behavioral code that is easy to verify and modify from scheduled designs such as pipeline architectures. We report four recent developments that significantly enhance the Haydn approach: (a) a design methodology that supports both cycle-accurate and behavioral levels, in which developers can move from one level to the other: (b) an extended scheduling algorithm which supports operation chaining, pipelined resources (with different latencies and initiation intervals), forwarding technique for loop-carried dependencies, and resource sharing and control; (c) a hardware design flow that can be customized with a script language and extended simulation capabilities for the RC2000 board; and (d) an evaluation of our approach using various case studies, including 3D free-form deformation (FFD), Gouraud shading, Fibonacci series, Montgomery multiplication, and one-dimensional DCT. For instance, our approach has been used to produce various FFD designs in hardware automatically; the smallest at 137 MHz is 294 times faster than software on a dual AMD MP2600+ processor machine at 2.1 GHz, and is 2.7 times smaller and 10% slower than the fastest design at 153 MHz.","PeriodicalId":222425,"journal":{"name":"13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130058361","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
Systolic architecture for computing the discrete Fourier transform on FPGAs fpga上离散傅里叶变换计算的收缩结构
13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05) Pub Date : 2005-04-18 DOI: 10.1109/FCCM.2005.60
J. Nash
{"title":"Systolic architecture for computing the discrete Fourier transform on FPGAs","authors":"J. Nash","doi":"10.1109/FCCM.2005.60","DOIUrl":"https://doi.org/10.1109/FCCM.2005.60","url":null,"abstract":"A systolic architecture for calculating the discrete Fourier transform (DFT) is described which is based on a new matrix formulation that decomposes the transform into sets of 4-point transforms. The architecture supports transform lengths that are not powers of two or based on products of coprime numbers. Compared to previous systolic implementations, the architecture is computationally more efficient and uses less hardware. It provides low latency as well as high throughput, and can do both 1D and 2D DFTs. An automated CAD tool was used to find latency and throughput optimal designs that matched the target field programmable gate array structure and functionality.","PeriodicalId":222425,"journal":{"name":"13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116950414","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
FIFO communication models in operating systems for reconfigurable computing 可重构计算操作系统中的FIFO通信模型
13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05) Pub Date : 2005-04-18 DOI: 10.1109/FCCM.2005.35
John A. Williams, N. Bergmann, Xin Xie
{"title":"FIFO communication models in operating systems for reconfigurable computing","authors":"John A. Williams, N. Bergmann, Xin Xie","doi":"10.1109/FCCM.2005.35","DOIUrl":"https://doi.org/10.1109/FCCM.2005.35","url":null,"abstract":"Increasing demands upon embedded systems for higher level services like networking, user interfaces and file system management, are driving growth in fully-featured operating systems such as embedded Linux. In reconfigurable system-on-chip (rSoC) design, a critical issue is efficient integration of custom hardware and software resources, where efficiency must be considered in terms of both design time and run time. Process networks communicating via FIFO queues are a powerful model for real time digital system design, especially for data streaming applications such as multimedia devices. FIFOs also form a central part of Unix and Linux interprocess communication (IPC) architectures, where they are more commonly known as pipes. In this paper, we expand on this observation and show how the combination of embedded Linux, reconfigurable system-on-chip, and FIFO communication models provide a compelling platform for efficient design- and run-time implementation of complex, high performance embedded systems.","PeriodicalId":222425,"journal":{"name":"13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05)","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122116328","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 27
An embedded reconfigurable datapath for SoC 用于SoC的嵌入式可重构数据路径
13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05) Pub Date : 2005-04-18 DOI: 10.1109/FCCM.2005.18
Andrea Lodi, L. Ciccarelli, C. Mucci, R. Giansante, A. Cappelli, M. Toma
{"title":"An embedded reconfigurable datapath for SoC","authors":"Andrea Lodi, L. Ciccarelli, C. Mucci, R. Giansante, A. Cappelli, M. Toma","doi":"10.1109/FCCM.2005.18","DOIUrl":"https://doi.org/10.1109/FCCM.2005.18","url":null,"abstract":"In this paper we present the new version of a multi-context reconfigurable datapath called PiCoGA (pipelined configurable gate array). The device provides a clear interface model and can be easily embedded in SoC systems where low power consumption and high computation capability are required. New logic cells and routing architecture have been designed for an efficient implementation of computation-intensive algorithms. The integration of a dedicated control unit for pipeline activity control provides a dataflow computational model which is easy to be integrated in a SoC. The embedded datapath has been designed using a 0.13 /spl mu/m CMOS technology. The implementation of several functions in the datapath achieves an average gate density of 1.3 KGates/mm/sup 2/ for each of the four available contexts.","PeriodicalId":222425,"journal":{"name":"13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129717200","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
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