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A comparison of floating point and logarithmic number systems for FPGAs fpga的浮点数和对数数系统的比较
13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05) Pub Date : 2005-04-18 DOI: 10.1109/FCCM.2005.6
M. Haselman, Michael J. Beauchamp, Aaron Wood, S. Hauck, K. Underwood, K. Hemmert
{"title":"A comparison of floating point and logarithmic number systems for FPGAs","authors":"M. Haselman, Michael J. Beauchamp, Aaron Wood, S. Hauck, K. Underwood, K. Hemmert","doi":"10.1109/FCCM.2005.6","DOIUrl":"https://doi.org/10.1109/FCCM.2005.6","url":null,"abstract":"There have been many papers proposing the use of logarithmic numbers (LNS) as an alternative to floating point because of simpler multiplication, division and exponentiation computations. However, this advantage comes at the cost of complicated, inexact addition and subtraction, as well as the need to convert between the formats. In this work, we created a parameterized LNS library of computational units and compared them to an existing floating point library. Specifically, we considered multiplication, division, addition, subtraction, and format conversion to determine when one format should be used over the other and when it is advantageous to change formats during a calculation.","PeriodicalId":222425,"journal":{"name":"13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128515018","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 64
Optimizing technology mapping for FPGAs using CAMs 利用凸轮优化fpga的技术映射
13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05) Pub Date : 2005-04-18 DOI: 10.1109/FCCM.2005.50
Joshua M. Lucas, R. Hoare, A. Jones
{"title":"Optimizing technology mapping for FPGAs using CAMs","authors":"Joshua M. Lucas, R. Hoare, A. Jones","doi":"10.1109/FCCM.2005.50","DOIUrl":"https://doi.org/10.1109/FCCM.2005.50","url":null,"abstract":"This paper describes an inexact string matching scheme devised to improve upon the LURU technique. The scheme uses a set of text strings called common subcircuit expressions (CSEs) to map a high percentage of the subcircuits in a netlist. The inexact matching scheme leverages the don't-care feature of ternary CAMs. Subcircuits are represented as standard-length strings that include wildcards. These strings are called homogeneous LURU strings (HLSs). LURU improves technology mapping by reducing the area requirements of LUT implementations. It also facilitates the profiling of circuits for the discovery of common subcircuits.","PeriodicalId":222425,"journal":{"name":"13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115803571","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Terrestrial-based radiation upsets: a cautionary tale 地面辐射扰乱:一个警示故事
13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05) Pub Date : 2005-04-18 DOI: 10.1109/FCCM.2005.61
H. Quinn, P. Graham
{"title":"Terrestrial-based radiation upsets: a cautionary tale","authors":"H. Quinn, P. Graham","doi":"10.1109/FCCM.2005.61","DOIUrl":"https://doi.org/10.1109/FCCM.2005.61","url":null,"abstract":"Problems with terrestrial-based neutron radiation from cosmic rays have become more commonplace. While the incident rate from neutron radiation is lower than space-based radiation, physics, system design and system locations have combined to make systems increasingly vulnerable to terrestrial radiation. FPGA systems are particularly sensitive to neutron radiation, as the FPGAs, microprocessors and memory are all sensitive to upsets. We are interested in reconfigurable supercomputers, which need to be highly reliable and highly available despite being very sensitive to radiation. In this paper, we estimate the error rate for FPGAs, memory, and microprocessors so that predictions for the sensitivity of the Cray XD1 reconfigurable supercomputer can be made. We also present possible mitigation methods that are appropriate for neutron radiation upset rates.","PeriodicalId":222425,"journal":{"name":"13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114812654","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 69
The GAPLA: a globally asynchronous locally synchronous FPGA architecture GAPLA:一个全局异步局部同步的FPGA架构
13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05) Pub Date : 2005-04-18 DOI: 10.1109/FCCM.2005.64
Xin Jia, R. Vemuri
{"title":"The GAPLA: a globally asynchronous locally synchronous FPGA architecture","authors":"Xin Jia, R. Vemuri","doi":"10.1109/FCCM.2005.64","DOIUrl":"https://doi.org/10.1109/FCCM.2005.64","url":null,"abstract":"This paper proposes GAPLA: a globally asynchronous locally synchronous programmable logic array architecture. The whole FPGA area is divided into locally synchronous blocks wrapped with asynchronous I/O interfaces. Data communications between synchronous blocks are controlled by 2-phase handshaking signals. The size and shape of each locally synchronous block are programmable so that different modules in a design can be effectively implemented. Each block could run at higher speed because only the fast local interconnections are used. Experimental results show an up to 28% performance improvement compared to the conventional FPGAs with small area overhead (around 2%).","PeriodicalId":222425,"journal":{"name":"13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05)","volume":"99 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127675710","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Simplifying the integration of processing elements in computing systems using a programmable controller 使用可编程控制器简化计算系统中处理元素的集成
13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05) Pub Date : 2005-04-18 DOI: 10.1109/FCCM.2005.59
Lesley Shannon, P. Chow
{"title":"Simplifying the integration of processing elements in computing systems using a programmable controller","authors":"Lesley Shannon, P. Chow","doi":"10.1109/FCCM.2005.59","DOIUrl":"https://doi.org/10.1109/FCCM.2005.59","url":null,"abstract":"As technology sizes decrease and die area increases, designers are creating increasingly complex computing systems using FPGAs. To reduce design time for new products, the reuse of previously designed intellectual property (IP) cores is essential. However, since no universally accepted interface standards exist for IP cores, there is often a certain amount of redesign necessary before they are incorporated into the new system. Furthermore, the core's functionality may need updating to support the requirements of the new application. This paper demonstrates how the SIMPPL system model allows designers to rapidly implement on-chip systems comprising multiple computing elements (CEs). Furthermore, using a controller-based interface to manage inter-CE transfers enables users to easily adapt the control sequence of individual CEs to suit the needs of new applications without necessitating the redesign of other elements in the system. Two systems using three different hardware modules adapted to CEs are described to illustrate the power and simplicity of the SIMPPL model. It required a total of six hours to implement both designs on-chip once the individual CEs had been designed.","PeriodicalId":222425,"journal":{"name":"13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05)","volume":"558 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126135623","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
FPGA-based vector processing for solving sparse sets of equations 基于fpga的向量处理求解稀疏方程组
13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05) Pub Date : 2005-04-18 DOI: 10.1109/FCCM.2005.38
M. Hasan, Sotirios G. Ziavras
{"title":"FPGA-based vector processing for solving sparse sets of equations","authors":"M. Hasan, Sotirios G. Ziavras","doi":"10.1109/FCCM.2005.38","DOIUrl":"https://doi.org/10.1109/FCCM.2005.38","url":null,"abstract":"The solution to a set of sparse linear equations Ax=b, where A is an n/spl times/n sparse matrix and b is an n-element vector, can be obtained using the W-matrix method. An enhanced vector processor is implemented on an FPGA for this problem. Performance results are presented. The effect of pipelined multiple functional units, multiple data buses, instruction chaining, hardware synchronization, pipelined scattering, matrix density, and distribution of non-zero elements is analyzed.","PeriodicalId":222425,"journal":{"name":"13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127073376","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
An execution environment for reconfigurable computing 用于可重构计算的执行环境
13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05) Pub Date : 2005-04-18 DOI: 10.1109/FCCM.2005.19
Wenyin Fu, Katherine Compton
{"title":"An execution environment for reconfigurable computing","authors":"Wenyin Fu, Katherine Compton","doi":"10.1109/FCCM.2005.19","DOIUrl":"https://doi.org/10.1109/FCCM.2005.19","url":null,"abstract":"Although many studies have demonstrated the benefits of reconfigurable computing, it has not yet penetrated the mainstream. One of the biggest unsolved problems is the management of the reconfigurable hardware in a multi-threaded environment. Most research in reconfigurable computing has assumed a single-threaded model, but this is unrealistic for personal computing and many types of embedded computing. In these cases, there may be several different threads or processes running simultaneously, each wishing to use the reconfigurable hardware. The operating system must decide how to allocate the hardware at run-time based on the status of the system. The system status could also influence the choice of different implementations for each circuit based on area/speed tradeoffs. This paper examines reconfigurable computing as it could be used in mainstream systems, focusing on a proposed scheduling algorithm to allocate the reconfigurable hardware. Our initial tests indicate that reconfigurable computing with our scheduler can easily achieve at least a 20% system-level speedup.","PeriodicalId":222425,"journal":{"name":"13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127514214","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 94
A BIST approach for testing FPGAs using JBITS 使用JBITS测试fpga的一种BIST方法
13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05) Pub Date : 2005-04-18 DOI: 10.1109/FCCM.2005.5
M. Niamat, Surya S. Hejeebu, Mansoor Alam
{"title":"A BIST approach for testing FPGAs using JBITS","authors":"M. Niamat, Surya S. Hejeebu, Mansoor Alam","doi":"10.1109/FCCM.2005.5","DOIUrl":"https://doi.org/10.1109/FCCM.2005.5","url":null,"abstract":"This paper explores the built-in self test (BIST) concepts to test the configurable logic blocks (CLBs) of static RAM (SRAM) based FPGAs using Java Bits (JBits). The proposed technique detects and diagnoses single and multiple stuck-at faults in the CLBs while significantly reducing the time taken to perform the testing. Previous BIST approaches for testing FPGAs use traditional CAD tools which lack control over configurable resources, resulting in the design being placed on the hardware in a different way than intended by the designer. In this paper, the design of the logic BIST architecture is done using JBits 2.8 software for Xilinx Virtex family of devices. The test requires seven configurations and two test sessions to test the CLBs. The time taken to generate the entire BIST logic in both the sessions is approximately 77 seconds as compared with several minutes to hours in traditional design flow.","PeriodicalId":222425,"journal":{"name":"13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131573025","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
High-performance FPGA-based general reduction methods 基于高性能fpga的通用约简方法
13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05) Pub Date : 2005-04-18 DOI: 10.1109/FCCM.2005.42
G. R. Morris, Ling Zhuo, V. Prasanna
{"title":"High-performance FPGA-based general reduction methods","authors":"G. R. Morris, Ling Zhuo, V. Prasanna","doi":"10.1109/FCCM.2005.42","DOIUrl":"https://doi.org/10.1109/FCCM.2005.42","url":null,"abstract":"FPGA-based floating-point kernels must exploit algorithmic parallelism and use deeply pipelined cores to gain a performance advantage over general-purpose processors. Inability to hide the latency of lengthy pipelines can significantly reduce the performance or impose unrealistic buffer requirements. Designs requiring reduction operations such as accumulation are particularly susceptible. In this paper we introduce two high-performance FPGA-based methods for reducing multiple sets of sequentially delivered floating-point values in optimal time without stalling the pipeline.","PeriodicalId":222425,"journal":{"name":"13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114346030","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
Design of networked reconfigurable encryption engine 网络可重构加密引擎的设计
13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05) Pub Date : 2005-04-18 DOI: 10.1109/FCCM.2005.30
Shakith Fernando, Yajun Ha
{"title":"Design of networked reconfigurable encryption engine","authors":"Shakith Fernando, Yajun Ha","doi":"10.1109/FCCM.2005.30","DOIUrl":"https://doi.org/10.1109/FCCM.2005.30","url":null,"abstract":"The current state-of-the-art has given rise to many potential networked appliances that would be able to download new hardware services and upgrades and execute them locally. However this technology has not been widely used. This paper describes a user scenario of networked reconfiguration in encryption application using embedded software and reconfigurable hardware. The appliance's hardware can be reconfigured at run-time, thus allowing to switch between several encryption standards and achieve hardware acceleration for each encryption standard. The reconfiguration bitstream is retrieved from the network, allowing future flexible scalability. A prototype has been built to demonstrate the functionality of the networked reconfigurable encryption engine.","PeriodicalId":222425,"journal":{"name":"13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05)","volume":"138 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123239214","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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