13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05)最新文献_第3页

A system-on-programmable chip approach for MIMO sphere decoder 一种用于MIMO球面解码器的系统-可编程芯片方法

13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05) Pub Date : 2005-04-18 DOI: 10.1109/FCCM.2005.13

Jing Ma, Xinming Huang

引用次数: 3

Time domain numerical simulation for transient waves on reconfigurable coprocessor platform 可重构协处理器平台上瞬态波时域数值模拟

13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05) Pub Date : 2005-04-18 DOI: 10.1109/FCCM.2005.65

Chuan He, Wei Zhao, Mi Lu

{"title":"Time domain numerical simulation for transient waves on reconfigurable coprocessor platform","authors":"Chuan He, Wei Zhao, Mi Lu","doi":"10.1109/FCCM.2005.65","DOIUrl":"https://doi.org/10.1109/FCCM.2005.65","url":null,"abstract":"A successful application-oriented reconfigurable coprocessor design requires not only a powerful FPGA-based computing engine along with suitable hardware architecture, but also an efficient algorithm tailored for this special application. In this paper, we present our hardware architecture and numerical algorithms designed to speedup the time-domain finite-difference simulation of linear wave propagation problems in 2D and 3D space on FPGA-based reconfigurable platforms. Application fields of this work include seismic modeling and migration, computational electromagnetics, aeroacoustics, marine acoustics, to name a few. By writing first-order linear wave equations into second-order form, we halve the number of unknowns and simplify the treatment of parameters. We also adopt higher-order finite-difference (FD) schemes to further reduce the number of unknowns at the cost of increasing floating-point computations per discrete grid point. By doing so, we relief the bandwidth requirements between the FPGA and onboard memories but put more burden on the computing engine to take full advantage of FPGA's computational potentials. The speed of our design implemented on a Xilinx ML401 Virtex-4 evaluation platform is about 1.5/spl sim/4 times faster than a pure software implementation of the same algorithm running on a 3.0 GHz DELL workstation. This impressive result is mainly attributed to the memory architecture design, which is well-tuned for our numerical higher-order FD algorithms and can utilize onboard memory bandwidth more wisely. Furthermore, the good scalability of our design makes it compatible with most commercial reconfigurable coprocessor platforms and correspondingly, the performance would be proportional to their onboard memory bandwidth.","PeriodicalId":222425,"journal":{"name":"13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114618524","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 35

A study of the scalability of on-chip routing for just-in-time FPGA compilation 面向FPGA实时编译的片上路由可扩展性研究

13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05) Pub Date : 2005-04-18 DOI: 10.1109/FCCM.2005.12

Roman L. Lysecky, F. Vahid, S. Tan

{"title":"A study of the scalability of on-chip routing for just-in-time FPGA compilation","authors":"Roman L. Lysecky, F. Vahid, S. Tan","doi":"10.1109/FCCM.2005.12","DOIUrl":"https://doi.org/10.1109/FCCM.2005.12","url":null,"abstract":"Just-in-time (JIT) compilation has been used in many applications to enable standard software binaries to execute on different underlying processor architectures. We previously introduced the concept of a standard hardware binary, using a just-in-time compiler to compile the hardware binary to a field-programmable gate array (FPGA). Our JIT compiler includes lean versions of technology mapping, placement, and routing algorithms, of which routing is the most computationally and memory expensive step. As FPGAs continue to increase in size, a JIT FPGA compiler must be capable of efficiently mapping increasingly larger hardware circuits. In this paper, we analyze the scalability of our lean on-chip router, the Riverside on-chip router (ROCR), for routing increasingly large hardware circuits. We demonstrate that ROCR scales well in terms of execution time, memory usage and circuit quality, and we compare the scalability of ROCR to the well known versatile place and route (VPR) timing-driven routing algorithm, comparing to both their standard routing algorithm and their fast routing algorithm. Our results show that on average ROCR executes 3 times faster using 18 times less memory than VPR. ROCR requires only 1% more routing resources, while creating a critical path 30% longer VPR's standard timing-driven router. Furthermore, for the largest hardware circuit, ROCR executes 3 times faster using 14 times less memory, and results in a critical path 2.6% shorter than VPR's fast timing-driven router.","PeriodicalId":222425,"journal":{"name":"13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05)","volume":"296 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115352318","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 29

Parallel hardware implementation of cellular learning automata based evolutionary computing (CLA-EC) on FPGA 基于进化计算的元胞学习自动机在FPGA上的并行硬件实现

13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05) Pub Date : 2005-04-18 DOI: 10.1109/FCCM.2005.51

A. Hariri, R. Rastegar, M. S. Zamani, M. Meybodi

引用次数: 9

An analysis of the double-precision floating-point FFT on FPGAs fpga上的双精度浮点FFT分析

13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05) Pub Date : 2005-04-18 DOI: 10.1109/FCCM.2005.16

K. Hemmert, K. Underwood

引用次数: 73

Post synthesis level power modeling of FPGAs fpga合成后级功率建模

13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05) Pub Date : 2005-04-18 DOI: 10.1109/FCCM.2005.53

M. French, Li Wang, T. Anderson, M. Wirthlin

引用次数: 16

Evaluation of code generation strategies for scalar replaced codes in fine-grain configurable architectures 细粒度可配置体系结构中标量替换代码的代码生成策略评估

13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05) Pub Date : 2005-04-18 DOI: 10.1109/FCCM.2005.32

P. Diniz

引用次数: 2

FPGA particle graphics hardware FPGA粒子图形硬件

13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05) Pub Date : 2005-04-18 DOI: 10.1109/FCCM.2005.36

J. S. Beeckler, W. Gross

引用次数: 12

A high-performance asynchronous FPGA: test results 一种高性能异步FPGA:测试结果

13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05) Pub Date : 2005-04-18 DOI: 10.1109/FCCM.2005.9

David Fang, J. Teifel, R. Manohar

引用次数: 26

A novel 2D filter design methodology for heterogeneous devices 一种新型的异构器件二维滤波器设计方法

13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05) Pub Date : 2005-04-18 DOI: 10.1109/FCCM.2005.10

C. Bouganis, G. Constantinides, P. Cheung

引用次数: 31