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13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05)最新文献

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The DARPA dynamic programming benchmark on a reconfigurable computer 在可重构计算机上的DARPA动态规划基准
13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05) Pub Date : 2005-04-18 DOI: 10.1109/FCCM.2005.62
L. E. Cordova, D. Buell, S. Akella
{"title":"The DARPA dynamic programming benchmark on a reconfigurable computer","authors":"L. E. Cordova, D. Buell, S. Akella","doi":"10.1109/FCCM.2005.62","DOIUrl":"https://doi.org/10.1109/FCCM.2005.62","url":null,"abstract":"The Defense Advanced Research Projects Agency (DARPA) has released high productivity computing systems (HPCS) benchmarks as specifications of performance required to solve important problems. This work reports on the design, implementation, and benchmarking of the benchmark number two, dynamic programming (DP), as developed in a general purpose reconfigurable computer. DP methods are used to solve DNA sequencing problems. DP has been also used successfully for optimal compression of barcode and other data, for control problems such as depth vision systems, and for chess endgames, among others. Clearly, it is helpful to know the application background; however, it is more important to note the benchmark is the product of a set of applications. Nonetheless it is intended to be developed and tested in a manner that is independent of any particular application.","PeriodicalId":222425,"journal":{"name":"13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05)","volume":"27 3-4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114027945","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Considering run-time reconfiguration overhead in task graph transformations for dynamically reconfigurable architectures 考虑动态可重构体系结构任务图转换中的运行时重构开销
13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05) Pub Date : 2005-04-18 DOI: 10.1109/FCCM.2005.28
Sudarshan Banerjee, E. Bozorgzadeh, N. Dutt
{"title":"Considering run-time reconfiguration overhead in task graph transformations for dynamically reconfigurable architectures","authors":"Sudarshan Banerjee, E. Bozorgzadeh, N. Dutt","doi":"10.1109/FCCM.2005.28","DOIUrl":"https://doi.org/10.1109/FCCM.2005.28","url":null,"abstract":"In modern dynamic FPGA-based platforms where multiple processes may be executing concurrently, partial dynamic reconfiguration (RTR) is a key technique for maximizing application performance under resource constraints. For platforms with column-based partial RTR, we propose a new technique to statically transform linear task graphs (common in image processing applications). In our approach, the granularity of data parallelism for each task is determined while considering the reconfiguration overhead along with architectural constraints imposed by partial RTR. On JPEG applications, our technique can improve the execution time by up to 37% by choosing the right granularity of task parallelism.","PeriodicalId":222425,"journal":{"name":"13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05)","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121419777","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Preliminary report: FPGA acceleration of molecular dynamics computations 初步报告:FPGA加速分子动力学计算
13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05) Pub Date : 2005-04-18 DOI: 10.1109/FCCM.2005.54
Y. Gu, T. Court, Douglas DiSabello, M. Herbordt
{"title":"Preliminary report: FPGA acceleration of molecular dynamics computations","authors":"Y. Gu, T. Court, Douglas DiSabello, M. Herbordt","doi":"10.1109/FCCM.2005.54","DOIUrl":"https://doi.org/10.1109/FCCM.2005.54","url":null,"abstract":"Molecular dynamics (MD) is of central importance to computational chemistry and its myriad applications. In this paper we show that, at even a preliminary stage of development, MD can be implemented efficiently on a COTS FPGA board, and that a 57x speed-up over a PC implementation can be obtained. We sketch our FPGA implementation and describe how performance tuning and precision management could double this factor.","PeriodicalId":222425,"journal":{"name":"13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05)","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114914312","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Register file architecture optimization in a coarse-grained reconfigurable architecture 在粗粒度的可重构体系结构中注册文件体系结构优化
13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05) Pub Date : 2005-04-18 DOI: 10.1109/FCCM.2005.58
Zion S. Kwok, S. Wilton
{"title":"Register file architecture optimization in a coarse-grained reconfigurable architecture","authors":"Zion S. Kwok, S. Wilton","doi":"10.1109/FCCM.2005.58","DOIUrl":"https://doi.org/10.1109/FCCM.2005.58","url":null,"abstract":"This paper investigates the impact of the local and global register file architecture on a reconfigurable system based on the ADRES architecture. The register files consume a significant amount of area on the reconfigurable device, and their architecture has a strong impact on the performance. We found that the global registers should be tightly connected to as many functional units as possible, while the connection of the local register files to their neighbours is less critical. We found that the global register file should contain between 12 and 16 registers, while each local register file should only contain one or two registers. We used these results to propose a new architecture that has between 60% and 95% higher performance per unit area compared to the original architecture over the set of benchmarks.","PeriodicalId":222425,"journal":{"name":"13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129798501","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 31
Metropolitan road traffic simulation on FPGAs 基于fpga的城市道路交通仿真
13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05) Pub Date : 2005-04-18 DOI: 10.1109/FCCM.2005.46
J. Tripp, H. Mortveit, A. Hansson, M. Gokhale
{"title":"Metropolitan road traffic simulation on FPGAs","authors":"J. Tripp, H. Mortveit, A. Hansson, M. Gokhale","doi":"10.1109/FCCM.2005.46","DOIUrl":"https://doi.org/10.1109/FCCM.2005.46","url":null,"abstract":"This work demonstrates that road traffic simulation of entire metropolitan areas is possible with reconfigurable supercomputing that combines 64-bit microprocessors and FPGAs in a high bandwidth, low latency interconnect. Previously, traffic simulation on FPGAs was limited to very-short road segments or required a very large number of FPGAs. Our data streaming approach overcomes scaling issues associated with direct implementations and still allows for high-level parallelism by dividing the data sets between hardware and software across the reconfigurable supercomputer. Using one FPGA on the Cray XD1 supercomputer, we are able to achieve a 34.4/spl times/ speed up over the AMD microprocessor. System integration issues must be optimized to exploit this speedup in the overall simulation.","PeriodicalId":222425,"journal":{"name":"13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05)","volume":"2 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130037584","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 37
A signature match processor architecture for network intrusion detection 一种网络入侵检测签名匹配处理器体系结构
13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05) Pub Date : 2005-04-18 DOI: 10.1109/FCCM.2005.11
Janardhan Singaraju, Long Bu, J. Chandy
{"title":"A signature match processor architecture for network intrusion detection","authors":"Janardhan Singaraju, Long Bu, J. Chandy","doi":"10.1109/FCCM.2005.11","DOIUrl":"https://doi.org/10.1109/FCCM.2005.11","url":null,"abstract":"In this paper, we introduce a novel architecture for a hardware based network intrusion detection system (NIDS). NIDSs are becoming critical components of the network infrastructure as they serve as a key line of defense in network protection. However, current methods are much too compute intensive and cannot begin to meet the bandwidth requirements of a moderate sized corporate network. Thus, hardware techniques are desired to speed up network processing. This paper introduces a FPGA based signature match processor that can serve as the core of a hardware based NIDS. The signature match processor's key feature is a CAM-based cellular processor architecture that can match strings in an area efficient manner. Using a unique binary tree structure, we are also able to generate priority encoded addresses corresponding to multiple signature matches.","PeriodicalId":222425,"journal":{"name":"13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129455175","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 33
A virtual machine for merit-based runtime reconfiguration 用于基于绩效的运行时重新配置的虚拟机
13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05) Pub Date : 2005-04-18 DOI: 10.1109/FCCM.2005.14
Brian Greskamp, R. Sass
{"title":"A virtual machine for merit-based runtime reconfiguration","authors":"Brian Greskamp, R. Sass","doi":"10.1109/FCCM.2005.14","DOIUrl":"https://doi.org/10.1109/FCCM.2005.14","url":null,"abstract":"This work advocates a merit-based reconfiguration policy. In the merit-based approach, each kernel that has a hardware implementation also has a software implementation. A runtime system performs continuous profiling of the application to decide which hardware reconfigurations are most profitable at any given time. Such a system can minimize thrashing, keeping the set of hardware-resident functionality constant over short intervals while still adapting to phased behavior in the application. Consequently, the system is better able to tolerate reconfiguration latencies. The main contribution of this work is the exhibition of a simple \"merit\" heuristic that can be used to direct reconfiguration. In this synopsis we present a brief overview of our ongoing work. First, a simple online algorithm for calculating a figure-of-merit for RTR systems is formalized. Next we describe its implementation and demonstrate a working prototype.","PeriodicalId":222425,"journal":{"name":"13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116760673","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
An open TCP/IP core for reconfigurable logic 一个开放的TCP/IP核心，用于重新配置逻辑
13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05) Pub Date : 2005-04-18 DOI: 10.1109/FCCM.2005.20
A. Dollas, Ioannis Ermis, Iosif Koidis, I. Zisis, C. Kachris
{"title":"An open TCP/IP core for reconfigurable logic","authors":"A. Dollas, Ioannis Ermis, Iosif Koidis, I. Zisis, C. Kachris","doi":"10.1109/FCCM.2005.20","DOIUrl":"https://doi.org/10.1109/FCCM.2005.20","url":null,"abstract":"This project is aimed at developing the full TCP/IP protocol as an open-source IP core which can be freely used, as well as to develop know-how on protocol boosting for complex protocols such as TCP/IP. The problem was quite challenging, especially if we consider that just about all commercial implementations of TCP/IP do not fully implement all of the protocol specifications.","PeriodicalId":222425,"journal":{"name":"13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116956117","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 38
RAVIOLI - reconfigurable arithmetic variable-precision implementations of on-line instructions 在线指令的可重构算术变精度实现
13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05) Pub Date : 2005-04-18 DOI: 10.1109/FCCM.2005.56
R. McIlhenny, M. Ercegovac
{"title":"RAVIOLI - reconfigurable arithmetic variable-precision implementations of on-line instructions","authors":"R. McIlhenny, M. Ercegovac","doi":"10.1109/FCCM.2005.56","DOIUrl":"https://doi.org/10.1109/FCCM.2005.56","url":null,"abstract":"In this paper, we present a library of floating-point arithmetic operators that can be dynamically reconfigured for either real-number or complex-number mode, and for which the precision is variable and is set prior to compilation. The library is compared to corresponding modules built using the Xilinx Alliance CORE library of floating-point arithmetic operators for the implementation of a unit that generates the inverse of a matrix. A significant lower cost and total cycle delay is demonstrated.","PeriodicalId":222425,"journal":{"name":"13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124215579","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
COMA: a cooperative management scheme for energy efficient implementation of real-time operating systems on FPGA based soft processors COMA:一种协作管理方案，用于在基于FPGA的软处理器上实现节能的实时操作系统
13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05) Pub Date : 2005-04-18 DOI: 10.1109/FCCM.2005.26
J. Ou, V. Prasanna
{"title":"COMA: a cooperative management scheme for energy efficient implementation of real-time operating systems on FPGA based soft processors","authors":"J. Ou, V. Prasanna","doi":"10.1109/FCCM.2005.26","DOIUrl":"https://doi.org/10.1109/FCCM.2005.26","url":null,"abstract":"FPGA based soft processors are an attractive choice for implementing many embedded systems. As real-time operating systems are adopted in the development of many applications using soft processors, we propose COMA, a cooperative management scheme in this paper for energy efficient implementation of real-time operating systems on soft processors. By utilizing the configurability of soft processors, we tightly couple several customized energy management hardware peripherals to them. These hardware peripherals cooperatively manage tasks and interrupts together with the processor while retaining the real-time responsiveness of the operating system. More specifically, they perform the following functionalities: (1) control the clock distribution network for driving the processor, the hardware peripherals and the communication interfaces between them; (2) take over the task and interrupt management responsibility of the operating system when the processor is shut off; (3) selectively wake up the processor and the corresponding hardware components for task execution based on the configurations of the processor and the hardware resource requirements of the tasks. We implement a real-time operating system on a popular soft processor to illustrate our approach. We show the development of an embedded application on the operating system enhanced with our energy management techniques. Actual measurements on an FPGA board demonstrates that our energy management scheme leads to energy reductions ranging from 73.3% to 89.9% and 86.8% on the average for the various execution scenarios considered in this paper.","PeriodicalId":222425,"journal":{"name":"13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131525325","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
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