Proceedings of the 2018 on Great Lakes Symposium on VLSI最新文献_第7页

Going Small: Using the Insect Brain as a Model System for Edge Processing Applications 走向小:使用昆虫大脑作为边缘处理应用的模型系统

Proceedings of the 2018 on Great Lakes Symposium on VLSI Pub Date : 2018-05-30 DOI: 10.1145/3194554.3194610

A. Yanguas-Gil

引用次数: 2

Impact of Aging on Template Attacks 老化对模板攻击的影响

Proceedings of the 2018 on Great Lakes Symposium on VLSI Pub Date : 2018-05-30 DOI: 10.1145/3194554.3194638

Naghmeh Karimi, S. Guilley, J. Danger

{"title":"Impact of Aging on Template Attacks","authors":"Naghmeh Karimi, S. Guilley, J. Danger","doi":"10.1145/3194554.3194638","DOIUrl":"https://doi.org/10.1145/3194554.3194638","url":null,"abstract":"Template attack is the most powerful side-channel attack from an information theoretic point of view. This attack is launched in two phases. In the first phase (training) the attacker uses a training device to estimate leakage models for targeted intermediate computations, which are then exploited in the second phase (matching) to extract secret information from the target device. Process variation and discrepancy of operating conditions (e.g., temperature) between training and matching phases adversely affect the success probability of the attack. Attack-success degradation is exacerbated when device aging comes into account. Due to aging, electrical specifications of transistors change over time. Thereby, if the training and target devices have experienced different usage time, the attack will be more difficult. Aging alignment between training and target devices is difficult as aging degradation is highly affected by operating conditions and technological variations. This paper investigates the effect of aging on the success rate of template attacks. In particular, we focus on NBTI and HCI aging mechanisms. We mount several attacks on the PRESENT cipher at different temperatures and aging times. Our results show that the attack is more difficult if there is an aging-duration mismatch between the training and target devices.","PeriodicalId":215940,"journal":{"name":"Proceedings of the 2018 on Great Lakes Symposium on VLSI","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125843408","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

MuDBN MuDBN

Proceedings of the 2018 on Great Lakes Symposium on VLSI Pub Date : 2018-05-30 DOI: 10.1145/3194554.3194630

Yuming Cheng, Chao Wang, Yangyang Zhao, Xianglan Chen, Xuehai Zhou, Xi Li

引用次数: 0

Leveraging Spintronic Devices for Efficient Approximate Logic and Stochastic Neural Networks 利用自旋电子器件实现高效近似逻辑和随机神经网络

Proceedings of the 2018 on Great Lakes Symposium on VLSI Pub Date : 2018-05-30 DOI: 10.1145/3194554.3194618

Shaahin Angizi, Zhezhi He, Y. Bai, Jie Han, Mingjie Lin, R. Demara, Deliang Fan

{"title":"Leveraging Spintronic Devices for Efficient Approximate Logic and Stochastic Neural Networks","authors":"Shaahin Angizi, Zhezhi He, Y. Bai, Jie Han, Mingjie Lin, R. Demara, Deliang Fan","doi":"10.1145/3194554.3194618","DOIUrl":"https://doi.org/10.1145/3194554.3194618","url":null,"abstract":"ITRS has identified nano-magnet based spintronic devices as promising post-CMOS technologies for information processing and data storage due to their ultra-low switching energy, non-volatility, superior endurance, excellent retention time, high integration density and compatibility with CMOS technology. As for data storage, spintronic memory has been widely accepted as a universal high performance next-generation non-volatile memory candidate. As for information processing, spintronic computing remains complementary in its features to CMOS technology. In this paper, we present two innovative spintronic computing primitives, i.e. spintronic approximate logic and spintronic stochastic neural network, which both leverage the intrinsic spintronic device physics to achieve much more compact and efficient designs than CMOS counterparts. In spintronic approximate logic, we employ the intrinsic current-mode thresholding operation to implement an accuracy-configurable adder and further demonstrate its application in approximate DSP applications. In spintronic stochastic neural networks, we leverage the stochastic properties of domain wall devices and magnetic tunnel junction to implement a low-power and robust artificial neural network design.","PeriodicalId":215940,"journal":{"name":"Proceedings of the 2018 on Great Lakes Symposium on VLSI","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127235016","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Session details: Session 4: Low Power Variation Aware Circuit Design 会议详情:会议4:低功耗变化感知电路设计

Proceedings of the 2018 on Great Lakes Symposium on VLSI Pub Date : 2018-05-30 DOI: 10.1145/3252911

Inna Partin-Vaisband

引用次数: 0

Innovating at Cloud Speed for IoT, AI, and Semiconductor Design 以云速度创新物联网、人工智能和半导体设计

Proceedings of the 2018 on Great Lakes Symposium on VLSI Pub Date : 2018-05-30 DOI: 10.1145/3194554.3200205

D. Pellerin

引用次数: 0

Bit-Wise Iterative Decoding of Polar Codes using Stochastic Computing 基于随机计算的极码逐位迭代译码

Proceedings of the 2018 on Great Lakes Symposium on VLSI Pub Date : 2018-05-30 DOI: 10.1145/3194554.3194620

Kaining Han, Junchao Wang, W. Gross

引用次数: 6

Cross-Layer Thermal Reliability Management in Silicon Photonic Networks-on-Chip 片上硅光子网络的跨层热可靠性管理

Proceedings of the 2018 on Great Lakes Symposium on VLSI Pub Date : 2018-05-30 DOI: 10.1145/3194554.3194608

S. Pasricha, S. V. R. Chittamuru, Ishan G. Thakkar

引用次数: 4

Fast Timing Analysis of Non-Tree Clock Network with Shorted Wires 短路非树时钟网络的快速时序分析

Proceedings of the 2018 on Great Lakes Symposium on VLSI Pub Date : 2018-05-30 DOI: 10.1145/3194554.3194598

Kiwon Yoon, Daijoon Hyun, Youngsoo Shin

{"title":"Fast Timing Analysis of Non-Tree Clock Network with Shorted Wires","authors":"Kiwon Yoon, Daijoon Hyun, Youngsoo Shin","doi":"10.1145/3194554.3194598","DOIUrl":"https://doi.org/10.1145/3194554.3194598","url":null,"abstract":"A non-tree clock network, such as crosslink and mesh, includes some shorted wires to reduce clock skew. A short-circuit current that flows through the shorted wires makes conventional static timing analysis (STA) inapplicable. Transistor-level simulation may be applied but takes long time. We address a fast timing analysis of non-tree clock network. A partial circuit made of drivers, shorted wires, and receivers is extracted and represented as voltagedependent current sources with π-model of RC load. Given voltage waveforms at driver inputs, we calculate the waveform at each shorted node by repeating nodal analysis for each time step; the waveform is represented as piecewise linear function. As the waveform propagates to receiver input via RC tree, the responses for all linear segments are obtained and merged into a full waveform. The waveform at receiver input then passes through receiver to produce a linear waveform at receiver output. Finally, timing parameters from the waveform at receiver output are transferred to STA, such that it utilizes the parameters to analyze the remaining circuit from receiver outputs to clock sinks. Experiments with a few test circuits demonstrate that analysis time is reduced by 10× with only 1% error on average (both in delay and transition time) compared to SPICE.","PeriodicalId":215940,"journal":{"name":"Proceedings of the 2018 on Great Lakes Symposium on VLSI","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121041680","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Investigation and Optimization of Pin Multiplexing in High-Level Synthesis 高阶合成中引脚复用的研究与优化

Proceedings of the 2018 on Great Lakes Symposium on VLSI Pub Date : 2018-05-30 DOI: 10.1145/3194554.3194629

Shuangnan Liu, F. Lau, Benjamin Carrión Schäfer

引用次数: 2