Proceedings of the 2018 on Great Lakes Symposium on VLSI最新文献_第8页

Assessing the Impact of Temperature and Supply Voltage Variations in Near-threshold Circuits using an Analytical Model 用分析模型评估近阈值电路中温度和电源电压变化的影响

Proceedings of the 2018 on Great Lakes Symposium on VLSI Pub Date : 2018-05-30 DOI: 10.1145/3194554.3194589

Sneh Saurabh, Vishav Vikash

{"title":"Assessing the Impact of Temperature and Supply Voltage Variations in Near-threshold Circuits using an Analytical Model","authors":"Sneh Saurabh, Vishav Vikash","doi":"10.1145/3194554.3194589","DOIUrl":"https://doi.org/10.1145/3194554.3194589","url":null,"abstract":"In this paper, we develop an analytical model based on Enz Krummenacher Vittoz (EKV) current equations to assess the impact of temperature and supply voltage (VDD) variations in circuits operating in near-threshold voltage (NTV) regime. Using the proposed model, we derive parameters that can be optimized to reduce the impact of these variations on devices operating in the NTV regime and highlight the dominant role of the inversion coefficient of the EKV equations. Further, we show that, instead of operating circuits such as a CMOS inverter very close to the threshold voltage (VTH.), it is beneficial to operate these circuits 3 - 4kT/q above the VTH. At these voltages, the impact of the temperature variations on the delay is minimized and the impact of VDD variations on delay is 0.7x lower than when operated at VDD =VTH. Additionally, compared to the super-threshold operation, the power consumption reduces by 5x and the delay increases by 5x. The results presented in this paper can be employed in estimating the increase in the time margins required when a circuit is migrated from the super-threshold operation to the near-threshold operation.","PeriodicalId":215940,"journal":{"name":"Proceedings of the 2018 on Great Lakes Symposium on VLSI","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128557799","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Improving the Security of Split Manufacturing Using a Novel BEOL Signal Selection Method 利用一种新的BEOL信号选择方法提高分离制造的安全性

Proceedings of the 2018 on Great Lakes Symposium on VLSI Pub Date : 2018-05-30 DOI: 10.1145/3194554.3194564

Suyuan Chen, R. Vemuri

引用次数: 7

Proceedings of the 2018 on Great Lakes Symposium on VLSI 2018五大湖VLSI研讨会论文集

Proceedings of the 2018 on Great Lakes Symposium on VLSI Pub Date : 2018-05-30 DOI: 10.1145/3194554

引用次数: 7

Adapting Convolutional Neural Networks for Indoor Localization with Smart Mobile Devices 基于卷积神经网络的智能移动设备室内定位

Proceedings of the 2018 on Great Lakes Symposium on VLSI Pub Date : 2018-05-30 DOI: 10.1145/3194554.3194594

Ayush Mittal, Saideep Tiku, S. Pasricha

引用次数: 54

DeEPeR 更深层次的

Proceedings of the 2018 on Great Lakes Symposium on VLSI Pub Date : 2018-05-30 DOI: 10.1145/3194554.3194566

M. Nikdast, G. Nicolescu, Jelena Trajkovic, O. Liboiron-Ladouceur

引用次数: 9

Battery-aware Design Exploration of Scheduling Policies for Multi-sensor Devices 多传感器设备调度策略的电池感知设计探索

Proceedings of the 2018 on Great Lakes Symposium on VLSI Pub Date : 2018-05-30 DOI: 10.1145/3194554.3194588

Yukai Chen, D. J. Pagliari, E. Macii, M. Poncino

{"title":"Battery-aware Design Exploration of Scheduling Policies for Multi-sensor Devices","authors":"Yukai Chen, D. J. Pagliari, E. Macii, M. Poncino","doi":"10.1145/3194554.3194588","DOIUrl":"https://doi.org/10.1145/3194554.3194588","url":null,"abstract":"Lifetime maximization is a key challenge in battery-powered multi-sensor devices. Battery-aware power management strategies combine task scheduling with dynamic voltage scaling (DVS), accounting for the fact that the power drawn by the device is different from that provided by the battery due to its many non-idealities. However, state-of-the-art techniques in this field do not take into account several important aspects, such as the impact of sensing tasks on the overall power demand, the (operating point dependent) losses due to multiple DC-DC conversions, and the dynamic modifications in battery efficiency caused by different distributions of the currents in the temporal and in the frequency domains. In this work, we propose a novel approach to identify optimal power management solutions, that addresses all these limitations. Specifically, using advanced battery and DC-DC converter models, we propose methods to explore the scheduling space both statically (at design time) and dynamically (at runtime), accounting not only for computation tasks, but also for communication and sensing. With this method, we show that the battery lifetime can be increased by as much as 23.36% if an optimal power management strategy is adopted.","PeriodicalId":215940,"journal":{"name":"Proceedings of the 2018 on Great Lakes Symposium on VLSI","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124177538","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 17

Challenges and Rewards of Implementing and Benchmarking Post-Quantum Cryptography in Hardware 在硬件中实现和基准测试后量子加密的挑战和回报

Proceedings of the 2018 on Great Lakes Symposium on VLSI Pub Date : 2018-05-30 DOI: 10.1145/3194554.3194615

K. Gaj

{"title":"Challenges and Rewards of Implementing and Benchmarking Post-Quantum Cryptography in Hardware","authors":"K. Gaj","doi":"10.1145/3194554.3194615","DOIUrl":"https://doi.org/10.1145/3194554.3194615","url":null,"abstract":"Practical quantum computers have been recently selected as one of 10 breakthrough technologies of 2017 by the MIT Technology Review. Although various fields of human activity, such as chemistry, medicine, and materials science, are likely to be dramatically affected by practical quantum computers, the most likely immediate impact will take place in the area of cryptography and cyber security. As a result of this potential threat, a new field of science has emerged, called Post-Quantum Cryptography (PQC). PQC is devoted to the design and analysis of cryptographic algorithms that are resistant against any known attacks using quantum computers, but by themselves can be implemented using classical computing platforms, based on traditional modern semiconductor technologies. In this paper, we provide an overview and motivation for the PQC, NIST Standardization Effort, cryptographic competitions, and hardware benchmarking of candidates in cryptographic contests. Five major families of PQC schemes, code-, hash-, isogeny-, lattice-, and multivariate-based, are shortly introduced. The challenges of fair and comprehensive hardware benchmarking of PQC submissions are highlighted, together with the possible ways of overcoming these difficulties, such as the use of a common API, development packages, specialized libraries, and high-level synthesis.","PeriodicalId":215940,"journal":{"name":"Proceedings of the 2018 on Great Lakes Symposium on VLSI","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127660961","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 12

New GPR System Integration with Augmented Reality Based Positioning 基于增强现实定位的新型GPR系统集成

Proceedings of the 2018 on Great Lakes Symposium on VLSI Pub Date : 2018-05-30 DOI: 10.1145/3194554.3194623

M. Pereira, D. Burns, D. Orfeo, Robert Farrel, D. Huston, Tian Xia

{"title":"New GPR System Integration with Augmented Reality Based Positioning","authors":"M. Pereira, D. Burns, D. Orfeo, Robert Farrel, D. Huston, Tian Xia","doi":"10.1145/3194554.3194623","DOIUrl":"https://doi.org/10.1145/3194554.3194623","url":null,"abstract":"The development of modern cities heavily relies on the availability and quality of underground utilities that provide drinking water, sewage, electric power, and telecommunication services to sustain its growing population. However, the information of localization and condition of subterranean infrastructures is generally not readily available, especially in areas with congested pipes, which impacts urban development, as poorly documented pipes may be hit during construction, affecting services and causing costly delays. Furthermore, aging components are prone to failure and may lead to resources waste or the interruption of services. Ground penetrating radar (GPR) is a promising remote sensing technique that has been recently used for mapping and assessment of underground infrastructure. However, current commercial GPR survey systems are designed with wheel-encoders or GPS for positioning. Wheel-encoder based GPR surveys are restrained to linear-route only, preventing the use of GPR for accurate localization of city wide underground infrastructure inspection. While GPS signal is degraded in urban canyons and unavailable in city tunnels. In this work, we present a new GPR system integration with augmented reality (AR) based positioning that can overcome the limitations of current GPR systems to enable arbitrary-route scanning with a high fidelity. It has the potential for automation of GPR survey and integration with AR smartphone applications that could be used for better planning in urban development.","PeriodicalId":215940,"journal":{"name":"Proceedings of the 2018 on Great Lakes Symposium on VLSI","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130909479","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 10

SCALENet SCALENet

Proceedings of the 2018 on Great Lakes Symposium on VLSI Pub Date : 2018-05-30 DOI: 10.1145/3194554.3194601

Colin Shea, A. Page, T. Mohsenin

{"title":"SCALENet","authors":"Colin Shea, A. Page, T. Mohsenin","doi":"10.1145/3194554.3194601","DOIUrl":"https://doi.org/10.1145/3194554.3194601","url":null,"abstract":"As deep learning networks mature and improve classification performance, a significant challenge is their deployment in embedded settings. Modern network typologies, such as convolutional neural networks, can be very deep and impose considerable complexity that is often not feasible in resource bound, real-time systems. Processing of these networks requires high levels of parallelization, maximizing data throughput, and support for different network types, while minimizing power and resource consumption. In response to these requirements, in this paper, we present a low power FPGA based neural network accelerator named SCALENet: a SCalable Low power AccELerator for real-time deep neural Networks. Key features include optimization for power with coarse and fine grain scheduler, implementation flexibility with hardware only or hardware/software co-design, and acceleration for both fully connected and convolutional layers. The experimental results evaluate SCALENet against two different neural network applications: image processing, and biomedical seizure detection. The image processing networks, implemented on SCALENet, trained on the CIFAR-10 and ImageNet datasets with eight different networks, are implemented on an Arty A7 and Zedboard#8482; FPGA platforms. The highest improvement came with the Inception network on an ImageNet dataset with a throughput of 22x and decrease in energy consumption of 13x compared to the ARM processor implementation. We then implement SCALENet for time series EEG seizure detection using both a Direct Convolution and FFT Convolution method to show its design versatility with a 99.7% reduction in execution time and a 97.9% improvement in energy consumption compared to the ARM. Finally, we demonstrate the ability to achieve parity with or exceed the energy efficiency of NVIDIA GPUs when evaluated against Jetson TK1 with embedded GPU System on Chip (SoC) and with a 4x power savings in a power envelope of 2.07 Watts.","PeriodicalId":215940,"journal":{"name":"Proceedings of the 2018 on Great Lakes Symposium on VLSI","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130077807","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11

Wavelength-Routed Optical Networks-on-Chip: Design Methods and Tools to Bridge the Gap Between Logic Topologies and Physical Ones in 3D Architectures 波长路由片上光网络:设计方法和工具，以弥合三维架构中逻辑拓扑和物理拓扑之间的差距

Proceedings of the 2018 on Great Lakes Symposium on VLSI Pub Date : 2018-05-30 DOI: 10.1145/3194554.3194607

D. Bertozzi, M. Gavanelli, M. Nonato

引用次数: 0