2008 IEEE International Conference on Electro/Information Technology最新文献

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Microcrystalline silicon-germanium solar cells fabricated using VHF PECVD 用甚高频PECVD制备的微晶硅锗太阳能电池
2008 IEEE International Conference on Electro/Information Technology Pub Date : 2008-05-18 DOI: 10.1109/EIT.2008.4554338
S. Saripalli, V. Dalal
{"title":"Microcrystalline silicon-germanium solar cells fabricated using VHF PECVD","authors":"S. Saripalli, V. Dalal","doi":"10.1109/EIT.2008.4554338","DOIUrl":"https://doi.org/10.1109/EIT.2008.4554338","url":null,"abstract":"We report on the properties of microcrystalline silicon-germanium (muc-Si1-xGex:H) alloy and solar cells fabricated using very high frequency plasma-enhanced chemical vapor deposition (VHF PECVD). p+nn+ structures are deposited at 275-300degC using mixtures of silane, 10%germane (rest is hydrogen) and hydrogen. Raman and XRD techniques were used to determine the crystalline nature of the films. From quantum efficiency data we observe enhanced infrared absorption with incorporation of germanium as compared to microcrystalline silicon (muc-Si:H) devices. The transport properties measured include minority carrier lifetime, diffusion length and mobility. The minority carrier lifetime values, measured using reverse recovery technique, in muc-Si1-xGex:H are found to be in the range of 150-250 ns. The diffusion length of holes measured in device structures was 0.5-2 mum, comparable to the typical values found in muc-Si:H. Hence, assuming a diffusion controlled transport, the estimated mobility, from diffusion length and lifetime measurements in muc-Si1-xGex:H is higher than that of muc-Si:H.","PeriodicalId":215400,"journal":{"name":"2008 IEEE International Conference on Electro/Information Technology","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114604659","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Complexes of on-line self assembly 在线自组装复合体
2008 IEEE International Conference on Electro/Information Technology Pub Date : 2008-05-18 DOI: 10.1109/EIT.2008.4554344
Neeraj Koul, J. Lathrop, J. H. Lutz, Vasant G Honavar
{"title":"Complexes of on-line self assembly","authors":"Neeraj Koul, J. Lathrop, J. H. Lutz, Vasant G Honavar","doi":"10.1109/EIT.2008.4554344","DOIUrl":"https://doi.org/10.1109/EIT.2008.4554344","url":null,"abstract":"The Tile Assembly Model (TAM) is a mathematical model of nanoscale self-assembly. In this paper we this model to define an on-line self assembly models called Fair Online Assembly(FOAF) and its variation called the Bounded Fair Online Assembly (FOAB). We show that these two models are not equivalent to each other. We also introduce the concepts of Binary and Trinary Complexes for a Tile Assembly System (TAS) and show if the complexes have a special property (called Frontier Turn Off Point-FTP) then the corresponding Self Assemblies are FOAF. Finally we argue that FOAF, FOAB and the size of the T-frontier at the frontier turn off point may be used to measure the complexity of the TAS.","PeriodicalId":215400,"journal":{"name":"2008 IEEE International Conference on Electro/Information Technology","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128549179","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Module Prototype for Online Failure Prediction for the IBM Blue Gene/L IBM Blue Gene/L在线故障预测模块原型
2008 IEEE International Conference on Electro/Information Technology Pub Date : 2008-05-18 DOI: 10.1109/EIT.2008.4554349
L. Solano-Quinde, Brett M. Bode
{"title":"Module Prototype for Online Failure Prediction for the IBM Blue Gene/L","authors":"L. Solano-Quinde, Brett M. Bode","doi":"10.1109/EIT.2008.4554349","DOIUrl":"https://doi.org/10.1109/EIT.2008.4554349","url":null,"abstract":"The growing complexity of scientific applications has led to the design and deployment of large-scale parallel systems. The IBM Blue Gene/L can hold in excess of 200 K processors and it has been designed for high performance and reliability. However, failures in this large-scale parallel system are a major concern, since it has been demonstrated that a failure will significantly reduce the performance of the system.","PeriodicalId":215400,"journal":{"name":"2008 IEEE International Conference on Electro/Information Technology","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134423979","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Reprogrammable high-speed platform : Bridging the gap between research, education and engineering 可重新编程的高速平台:弥合研究、教育和工程之间的差距
2008 IEEE International Conference on Electro/Information Technology Pub Date : 2008-05-18 DOI: 10.1109/EIT.2008.4554283
Jin-Wei Tioh, R. Bahuguna, N. VanderHorn, M. Mina, R. Weber, Arun Kumar Somani
{"title":"Reprogrammable high-speed platform : Bridging the gap between research, education and engineering","authors":"Jin-Wei Tioh, R. Bahuguna, N. VanderHorn, M. Mina, R. Weber, Arun Kumar Somani","doi":"10.1109/EIT.2008.4554283","DOIUrl":"https://doi.org/10.1109/EIT.2008.4554283","url":null,"abstract":"In order to keep pace with advancements in technology, electrical and computer engineering education is undergoing some major changes. Today's students are utilizing more sophisticated equipment in the classroom and laboratory to enhance their engineering skills. Much of this change is fueled by the availability of more affordable and easy to use microcontrollers and embedded systems including reconfigurable multipurpose hardware platforms. At the heart of this paradigm shift in education is the proliferation of field programmable gate arrays (FPGAs), programmable logic devices (PLDs) and the growth of system on a chip (SOC) design. SOC designs facilitate innovation by incorporating the speed of dedicated hardware and memory with the flexibility of general purpose processors on a single chip. The use of this prototyping platform is enabling students to combine information form courses in digital logic design and microcontroller programming to create system-level designs and more fully understand hardware / software interaction. In this paper we provide a background of the reprogrammable platform and discuss how academic research activities can also benefit from the use of a similar platform. By enhancing information sharing and cooperation between research and education undergraduate students can gain more exposure to cutting-edge academic research. In addition, the use of prototyping for research will provide additional visibility of research projects to the industrial community. We suggest, through the use of case studies utilizing the reprogrammable platform how such cooperation can be achieved and prove beneficial to technology development.","PeriodicalId":215400,"journal":{"name":"2008 IEEE International Conference on Electro/Information Technology","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133446986","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Vapor HF sacrificial etching for phosphorus doped polycrystalline silicon membrane structures 磷掺杂多晶硅膜结构的气相HF牺牲蚀刻
2008 IEEE International Conference on Electro/Information Technology Pub Date : 2008-05-18 DOI: 10.1109/EIT.2008.4554316
H. Cao, R. Weber
{"title":"Vapor HF sacrificial etching for phosphorus doped polycrystalline silicon membrane structures","authors":"H. Cao, R. Weber","doi":"10.1109/EIT.2008.4554316","DOIUrl":"https://doi.org/10.1109/EIT.2008.4554316","url":null,"abstract":"In this work we present a technique using HF vapor to release phosphorus doped polycrystalline silicon (Phos-Poly) circular membrane structures. A 2 um thick annealed phosphosilicate glass (PSG) has been used as the sacrificial layer. The sacrificial etching was followed by solvent rinses and Critical Point Drying (CPD) to remove any residual HF and to avoid sticition. A Phos-Poly diaphragm with a diameter of 106 um has been successfully released as well as some membrane arrays. This technique has been proved very simple and effective. The membrane structures can be used in pressure sensing applications.","PeriodicalId":215400,"journal":{"name":"2008 IEEE International Conference on Electro/Information Technology","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116798039","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Architectural support for securing application data in embedded systems 在嵌入式系统中保护应用程序数据的体系结构支持
2008 IEEE International Conference on Electro/Information Technology Pub Date : 2008-05-18 DOI: 10.1109/EIT.2008.4554261
Olga Gelbart, Eugen Leontie, B. Narahari, R. Simha
{"title":"Architectural support for securing application data in embedded systems","authors":"Olga Gelbart, Eugen Leontie, B. Narahari, R. Simha","doi":"10.1109/EIT.2008.4554261","DOIUrl":"https://doi.org/10.1109/EIT.2008.4554261","url":null,"abstract":"The rapid growth and pervasive use of embedded systems makes it easier for an adversary to gain physical access to these devices to launch attacks and reverse engineer of the system. Encrypted execution and data (EED) platforms, where instructions and data are stored in encrypted form in memory, while incurring overheads of encryption have proven to be attractive because they offer strong security against information leakage and tampering. However, several attacks are still possible on EED systems when the adversary gains physical access to the system. In this paper we present an architectural approach to address a class of memory spoofing attacks, in which an attacker can control the address bus and spoof memory blocks as they are loaded into the processor. In this paper we focus on the integrity of the application data to prevent the attacker from tampering, injecting or replaying the data. We make use of an on-chip FPGA, an architecture that is now commonly available on many processor chips, to build a secure on-chip hardware component that verifies the integrity of application data at run-time. By implementing all our security primitives on the FPGA we do not require changes to the processor architecture. We present that data protection techniques and a performance analysis is provided through a simulation on a number of bechmarks. Our experimental results show that a high level of security can be achieved with low performance overhead.","PeriodicalId":215400,"journal":{"name":"2008 IEEE International Conference on Electro/Information Technology","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124134240","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Orthogonal coding and iterative decoding improves coding gain 正交编码和迭代译码提高了编码增益
2008 IEEE International Conference on Electro/Information Technology Pub Date : 2008-05-18 DOI: 10.1109/EIT.2008.4554313
S. Faruque
{"title":"Orthogonal coding and iterative decoding improves coding gain","authors":"S. Faruque","doi":"10.1109/EIT.2008.4554313","DOIUrl":"https://doi.org/10.1109/EIT.2008.4554313","url":null,"abstract":"This paper shows that orthogonal coding and iterative decoding improve coding gain. The encoder maps a block of data into a block of bi-orthogonal codes. The decoder is a correlation receiver, which performs iterative decoding to reduce the error and enhance the coding gain. To illustrate this concept, BER performance analysis of rate frac12 orthogonal coding and iterative decoding is presented.","PeriodicalId":215400,"journal":{"name":"2008 IEEE International Conference on Electro/Information Technology","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124379809","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An adaptive fuzzy thresholding algorithm for exon prediction 外显子预测的自适应模糊阈值算法
2008 IEEE International Conference on Electro/Information Technology Pub Date : 2008-05-18 DOI: 10.1109/EIT.2008.4554298
Ankit Agrawal, A. Mittal, Rahul Jain, R. Takkar
{"title":"An adaptive fuzzy thresholding algorithm for exon prediction","authors":"Ankit Agrawal, A. Mittal, Rahul Jain, R. Takkar","doi":"10.1109/EIT.2008.4554298","DOIUrl":"https://doi.org/10.1109/EIT.2008.4554298","url":null,"abstract":"Thresholding is always critical and decisive in problem solving. In this paper, we propose an adaptive fuzzy logic-based approach to thresholding for exon prediction problem, which is an important problem in bioinformatics. Rather than using the same threshold for the entire dataset, we allow the thresholds to vary along the dataset based on the local statistical properties. We incorporate it in a soft computing framework of training and testing to determine the optimum adaptive thresholds. The search space of the trained database is reduced by determining a dynamic range of thresholds using fuzzy logic rules, which makes our approach faster. To test our approach, we applied the proposed algorithm on a particular solution to the exon prediction problem, which uses a threshold on the frequency component at f = 1/3 in the nucleotide sequences. Preliminary experiments on the nucleotide data of Saccharomyces Cerevisiae (Bakers yeast) illustrate the potential of our approach. The adaptive thresholding approach gave suitable thresholds to detect the exons which were otherwise difficult to detect using a traditional static thresholding scheme.","PeriodicalId":215400,"journal":{"name":"2008 IEEE International Conference on Electro/Information Technology","volume":"83 10","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113940749","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Simulation of a cyclic multicast proxy server 模拟循环组播代理服务器
2008 IEEE International Conference on Electro/Information Technology Pub Date : 2008-05-18 DOI: 10.1109/EIT.2008.4554275
O. Abiona, T. Anjali, L. Kehinde
{"title":"Simulation of a cyclic multicast proxy server","authors":"O. Abiona, T. Anjali, L. Kehinde","doi":"10.1109/EIT.2008.4554275","DOIUrl":"https://doi.org/10.1109/EIT.2008.4554275","url":null,"abstract":"The exponential growth of the World Wide Web (WWW) users has made the deployment of proxy servers popular on a network with limited resources. WWW clients perceive better response time, improved performance and speed when response to requested pages are served from the cache of a proxy server, resulting in faster response times after the first document fetch. This work focuses on the development of a cyclic multicast proxy server through the use of a cyclic multicast engine for the delivery of popular web pages from the proxy server cache to increasingly large users under limited server capacity and network resources. The cyclic multicast technique would be more efficient for the delivery of highly requested web pages from the cache to large numbers of receivers. We describe the operation of the cyclic multicast proxy server and characterized the gains in performance through simulation of the cyclic multicast proxy server.","PeriodicalId":215400,"journal":{"name":"2008 IEEE International Conference on Electro/Information Technology","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127232120","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Collaboration framework for data compensation in sensor networks 传感器网络数据补偿协同框架
2008 IEEE International Conference on Electro/Information Technology Pub Date : 2008-05-18 DOI: 10.1109/EIT.2008.4554355
P. Tiako, L. Gruenwald
{"title":"Collaboration framework for data compensation in sensor networks","authors":"P. Tiako, L. Gruenwald","doi":"10.1109/EIT.2008.4554355","DOIUrl":"https://doi.org/10.1109/EIT.2008.4554355","url":null,"abstract":"This paper proposes a new approach of modeling the collaboration of sensor system artifacts to address the security and survivability concerns of sensor networks. The model considered is composed of sensors, base and users. Sensors are nodes that acquire and process data. Base is the node that acquires and processes data from sensors and provides an interface to access and monitor the sensor network while users monitor the system. The model proposed is instantiated and validated using association rule mining to compensate missing data in order to provide security and survivability to sensor networks.","PeriodicalId":215400,"journal":{"name":"2008 IEEE International Conference on Electro/Information Technology","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125677241","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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