Workshop on VLSI Signal Processing最新文献

{"title":"An Algorithmic Approach To Concurrent Error Detection In Artificial Neural Networks","authors":"V. Piuri","doi":"10.1109/VLSISP.1992.641084","DOIUrl":"https://doi.org/10.1109/VLSISP.1992.641084","url":null,"abstract":"Fault tolerance is a basic issue for VLSI implementation of artificial neural networks dedicated to mission-critical applications. In this paper, we propose a high-level approach to concurrent error detection: our technique is based upon the behavioral definition of the neural computation and abstracts from the specific architectural and technological implementation.","PeriodicalId":210565,"journal":{"name":"Workshop on VLSI Signal Processing","volume":"100 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121473505","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Tri-array For The Real-time Computation Of Higher Order Moment Estimates","authors":"H.M. Stellakis, E. Manolakos","doi":"10.1109/VLSISP.1992.641082","DOIUrl":"https://doi.org/10.1109/VLSISP.1992.641082","url":null,"abstract":"Abstarct To achieve real-time performance in signal processing applications that require the computation of Higher Order Statistics, it is necessary to employ parallel and pipelined processing. We propose a triangular scalable VLSI array architecture that can produce the positive lags of all the moments, up to the fourth order, of an one-dimensional real data sequence. The array may be extended to provide also real-time estimation of Higher Order Cumulants and the associated Polyspectra. A systematic algorithm-to-architectures direct mapping methodology was employed to And all the solutions that meet the usual VLSI design constraints and performance specifications. The proposed array achieves minimum latency and maximum processor utilization.","PeriodicalId":210565,"journal":{"name":"Workshop on VLSI Signal Processing","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114219806","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"An Approach For Power Minimization Using Transformations","authors":"A. Chandrakasan, M. Potkonjak, J. Rabaey, R. Brodersen","doi":"10.1109/VLSISP.1992.639171","DOIUrl":"https://doi.org/10.1109/VLSISP.1992.639171","url":null,"abstract":"An approach is presented for minimizing power consumption in algorithm AN APPROACH FOR POWER MINIMIZATION USING TRANSFORMATIONS iantha Chandrakasan?, Miodrag Potkonjak??, Jan Rabaey?, Robert Broderseri? ?EECS Department, University of California at Berkeley. ?+C & C Research Laboratories, NEC USA, Princeton.","PeriodicalId":210565,"journal":{"name":"Workshop on VLSI Signal Processing","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129278977","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Cellular Broadcast In Regular Processor Arrays","authors":"E. Deprettere","doi":"10.1109/VLSISP.1992.641064","DOIUrl":"https://doi.org/10.1109/VLSISP.1992.641064","url":null,"abstract":"","PeriodicalId":210565,"journal":{"name":"Workshop on VLSI Signal Processing","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126411871","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"An Adaptive High-speed Vector Quantization","authors":"O. Chen, Zhen Zhang, B. Sheu","doi":"10.1109/VLSISP.1992.641053","DOIUrl":"https://doi.org/10.1109/VLSISP.1992.641053","url":null,"abstract":"An adaptive method for vector quantization and the associated VLSI architecture are presented. This method does not require Qpriori knowledge of the source statistics and codebook training. The codebook is generated on the fly and is constantly updated to capture local textual features of data. ‘fhe algorithm is shown to reacli rate distortion function for menioryless sources. We also propose a computation architecture which consists of two move-to-front vector quantizers and an index generator. The processing element i n the moue-to-front vector quantizer is designed by using a 0.5 pni CMOS technology. The total transistor count can be about 10,000. I t can provide a computing capability of 200M pixels per second for I@-speed iniage compression systems. Ily using this method, a high-speed VLSI processor with good local adaptivity, reduced complexity, and Pdirly good conipression ratio can be achieved. INTRODUCTION Efficient compression of data would significantly decrease both the communication and archival costs [1,21. A fundamental result of Shannon’s ratcdistortion thcory [ 3 ] states that bcttcr pcrformancc can always bc achieved by coding vectors instcad of scalars. Vcctor quantization [4] is a process in which data are divided into sinall vcctors, which are then individually encoded in scqucnce. Thc objective is to idcntify a sct of possible vectors which are representative of thc information to be encoded. Vector quantization is a very cffcctive tcchniquc for specch waveform coding and image data compression 15.61. Rccently, Lhcorctical foundation for a new vector-quantization-based lossy data compression approach was reported [7]. This adaptive vector quantization (AVQ) does not need any a-priori knowledge of thc source statistics. The codebook is generated on the fly as the data flow in. Thcre is no separate codcbook mining or preprocessing before the actual vcctor quantization. The codcbook is constantly updated in order to capture the local textual features of thc dala. In the VLSI design, the main circuit modules arc an array conwoller, two movc-to-front vector quantizers (MFVQ) and an index gcnerator. The source data arc piped into the two move-to-front vector quantizers and then the index generator calculates the index value from the output rcsulb of the two MFVQs. If thcre exists a codcvector which can meet the distortion requirement, h e output index value and an identification code form the compressed d a h If not, the host machine uses the block-data This rescarch was paaially supponed by NSI: under Grant No. NU<-8905052, and by DARPA under Contract No. MDA 972-90-C-0037.","PeriodicalId":210565,"journal":{"name":"Workshop on VLSI Signal Processing","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131446487","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Column Compression Multipliers For Signal Processing Applications","authors":"Zhongde Wang, G. Jullien, W. Miller","doi":"10.1109/VLSISP.1992.639174","DOIUrl":"https://doi.org/10.1109/VLSISP.1992.639174","url":null,"abstract":"An improved architecture for column-compression (CC) milltipliers is proposed; this architecture is targeted to applications in high performance signal processing. Constraints for column compression with full and half adders are analyzed, and, under these constraints, considerable flexibility for the realization of a new CC multiplier architecture is exposed. Using the example of an 8x8 bit CC multiplier, we show that this new architecture is more area efficient, and has shorter interconnections than the Dadda multiplier.","PeriodicalId":210565,"journal":{"name":"Workshop on VLSI Signal Processing","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117085725","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Simd Dsp For Real-time Mpeg Video Encoding And Decodiing","authors":"I. Tamitani, A. Yoshida, Y. Ooi, T. Nishitani","doi":"10.1109/VLSISP.1992.641044","DOIUrl":"https://doi.org/10.1109/VLSISP.1992.641044","url":null,"abstract":"A.bstract This paper presents a single-chip 480 MOPS programmable LISP used in a real-time MPEG/H.261 video codec chip set. The DSP plerforms discrete cosine transform (DCT), quantization, and other arithmtetic processing by software control. To achieve t.hese calculations in real-time, the chip employs four single-instruction multiple-data (SIMD) processing units (PUS), each of which is composed of multiply-accumulator (MAC), ALU, and registers. For fast DCT calculation, the PU achieves butterfly operations as well as inner-products in parallel. Single-step data-dependent operations are newly introduced for efflcient quantizer implementation under SIMD control. With these features real-time M:PEG/H.261 encoding of a 352 pels x 288 lines 30 frames/sec video sequence is accomplished.","PeriodicalId":210565,"journal":{"name":"Workshop on VLSI Signal Processing","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115538484","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Clustering Approach For Mapping Recursive Dsp Algorithms To Multiprocessor With Fixed Ipc Delays","authors":"Y. Hu, Duen-Jeng Wang","doi":"10.1109/VLSISP.1992.641068","DOIUrl":"https://doi.org/10.1109/VLSISP.1992.641068","url":null,"abstract":"","PeriodicalId":210565,"journal":{"name":"Workshop on VLSI Signal Processing","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126808063","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Systolic Implementation Of The Regularized Parameter Estimator","authors":"J. Kadlec, F. Gaston, G. Irwin","doi":"10.1109/VLSISP.1992.641083","DOIUrl":"https://doi.org/10.1109/VLSISP.1992.641083","url":null,"abstract":"","PeriodicalId":210565,"journal":{"name":"Workshop on VLSI Signal Processing","volume":"67 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129870303","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Architectures For Integration Of Real Time Image Processing Systems","authors":"M. Robert, Michel Paindavoine, P. Gorria","doi":"10.1109/VLSISP.1992.641059","DOIUrl":"https://doi.org/10.1109/VLSISP.1992.641059","url":null,"abstract":"We present the design of a low-cost and real-time image processing microsystem to detect defects on manufacturing products. The analysis method is based on an edge detection algorithm (differential operators) to select the information related to the structure of objects present in the image, associated to a parallel processor for image classification. The circuits have been developed in a cell based approach, using a CMOS 1.5pm process.","PeriodicalId":210565,"journal":{"name":"Workshop on VLSI Signal Processing","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130215637","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}