Workshop on VLSI Signal Processing最新文献_第5页

Vlsi Systolic Array Implementation Of A Staged Decoder For Bcm Signals Bcm信号分级解码器的Vlsi收缩阵列实现

Workshop on VLSI Signal Processing Pub Date : 1992-10-28 DOI: 10.1109/VLSISP.1992.641046

G. Caire, J. Ventura-Traveset, J. Murphy, S. Kung

引用次数: 1

A Systematic Folding Design Procedure For a1-D RLs Systolic Array 一维RLs收缩阵列的系统折叠设计

Workshop on VLSI Signal Processing Pub Date : 1992-10-28 DOI: 10.1109/VLSISP.1992.641078

F. Lorenzelli, K. Yao

{"title":"A Systematic Folding Design Procedure For a1-D RLs Systolic Array","authors":"F. Lorenzelli, K. Yao","doi":"10.1109/VLSISP.1992.641078","DOIUrl":"https://doi.org/10.1109/VLSISP.1992.641078","url":null,"abstract":"Classical systolic design procedures rely on lineair or affine space-time transformations, because of the well understood properties of linear operations. In order to increase the efficiency of the Anal processor, various ad hoc manipulations applied to transformations which appeared to be nonlinear at the physical array level have been ,proposed. Folding is one of these possible transformations. In this paper, we show that folding can actually be considered as an overall linear procedure, by artificially increasing the dimensionality of the dependence graiph of the algorithm. A one-dimensional array for recursive least squares is also derived, as application of a systematic linear design procedure including folding. INTRODUCTION Recursive least squares (RLS) problems appear in a large number of signal processing applications. In this paper, a one-dimensional array for RLS problems is derived using a systematic systolic design. By means of an artificial increase of the dimensionality of the dependence graph of the <algorithm, folding is included in the design procedure, without losing the linearity of the methodology. An example of the use of RLS for an adaptive antenna application has been considered by Rader in [lo]. The signals arriving at n antenna ports are sampled and stored in a matrix X ( t ) E IR\"\". At any time instant, a new row of data is appended to X . The output y ( t ) is a weighted sum of the inputs, i . e . , y(t) = X ( t ) w . The problem consists of determining the weights w E IR\" and updating them at given times (say, eveiry 5n new sample times). The desired weight vector satisfies the property of","PeriodicalId":210565,"journal":{"name":"Workshop on VLSI Signal Processing","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125328055","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Automating High Level Control F'low Transformations For Dsp Memory Management 用于Dsp内存管理的高级控制转换自动化

Workshop on VLSI Signal Processing Pub Date : 1992-10-28 DOI: 10.1109/VLSISP.1992.641071

M.F.X.B. van Swaaij, F. Franssen, F. Catthoor, H. de Man

引用次数: 40

A Data-driven Architecture For Rapid Prototyping Of High Throughput Dsp Algorithms 一种数据驱动的高吞吐量Dsp算法快速原型设计体系结构

Workshop on VLSI Signal Processing Pub Date : 1992-10-28 DOI: 10.1109/VLSISP.1992.641055

A. Yeung, J. Rabaey

引用次数: 14

VLSI Implementation Of The Realtime Image Processing Parallel Architecture Gflops 实时图像处理并行架构的VLSI实现

Workshop on VLSI Signal Processing Pub Date : 1992-10-28 DOI: 10.1109/VLSISP.1992.641049

D. Houzet

引用次数: 3

Morphological Image Processing On Vlsi Opto-electronic Array Processors 基于Vlsi光电阵列处理器的形态图像处理

Workshop on VLSI Signal Processing Pub Date : 1992-10-28 DOI: 10.1109/VLSISP.1992.641060

W. Fang, T. Shaw, J. Yu

引用次数: 0

Vlsi Architectures And Implementation Of Predictive Tree-searched Vector Quantizes For Real-time Video Compression 用于实时视频压缩的预测树搜索矢量量化的Vlsi架构和实现

Workshop on VLSI Signal Processing Pub Date : 1992-10-28 DOI: 10.1109/VLSISP.1992.641057

S. Yu, R. Kolagotla, J. JáJá

引用次数: 0

Piecewise Linear Schedules For Recurrence Equations 递归方程的分段线性调度

Workshop on VLSI Signal Processing Pub Date : 1992-10-28 DOI: 10.1109/VLSISP.1992.641069

S. Rajopadhye, L. Mui, S. Kiaei

引用次数: 6

A Concurrent Losslesss Coder For Video Compression 用于视频压缩的并发无损编码器

Workshop on VLSI Signal Processing Pub Date : 1900-01-01 DOI: 10.1109/VLSISP.1992.641058

K. Parhi, G. Shrimali

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引用次数: 3