A Data-driven Architecture For Rapid Prototyping Of High Throughput Dsp Algorithms

Abstract

A data-driven multiprocessor architecture for rapid prototyping of complex DSP algorithms, based on direct execution of data-flow graphs, is presented. High computation bandwidth is achieved by exploiting fine-grain parallelism inherent in the target algorithms using simple processing elements interconnected by a flexible static communication network. The use of distributed control and data-driven principle of execution results in a highly scalable and modular architecture. A prototype chip, which is being designed, will contain 64 nanoprocessors and provide 32 GOPS running at 50 MHz. The benchmark results based on a variety of DSP algorithms in video processing, digital communication, digital filtering and speech recognition confirm the performance, efficiency and generality of the architecture.