Workshop on VLSI Signal Processing最新文献

A Vlsi Algorithm For Svd Tracking Svd跟踪的Vlsi算法

Workshop on VLSI Signal Processing Pub Date : 1992-10-28 DOI: 10.1109/VLSISP.1992.641075

E.M. DowIing, L. Ammann, R.D. DeGroat

引用次数: 1

Sisim: A System-level Interactive Simulator For Array Processor System 阵列处理器系统级交互模拟器

Workshop on VLSI Signal Processing Pub Date : 1992-10-28 DOI: 10.1109/VLSISP.1992.641070

W.H. Chouand, S. Kung

{"title":"Sisim: A System-level Interactive Simulator For Array Processor System","authors":"W.H. Chouand, S. Kung","doi":"10.1109/VLSISP.1992.641070","DOIUrl":"https://doi.org/10.1109/VLSISP.1992.641070","url":null,"abstract":"A system-level simulation is critical to prevent designers from wasting time on the lower level design for an incorrect specification. I t is also needed to evaluate the performance of the final implementation. In this paper, a system-level interactive simulator, SISim, for array processor system is proposed. The hardware and software specification modules for SISim are introduced. The simulation mechanism based on an event-driven scheme is discussed. The interactive mode of SISim is described. Then, an example for implementing a two-layer Binck Propagation Neural Network on array processors is given. Some future work is also included. INTRODUCTION Due to the VLSI technology developed in these years, the algorithm-based architecture design which requires huge amount of memory, communication and computation power has become feasible. Multiprocessors, array processors, or massively parallel processors are the most appealing architectures. Although many techniques have been developed to map an algorithm onto an array processor (cf. [l] [2] [5] [6]), it still lacks automatic design tools to help designing a multiprocessor system effectively and efficiently. In the systemlevel design, simulation is often used to discover the relationship between the performance and some design parameters of the system. In order to get an accurate information about the behavior of a system, both the hardware and software must be specified precisely (cf, [a]). The hardware specification for a multiprocessor system should describe the configuration of the whole system and also the hardware components of each processor. The software specification should describe the work of each processor corresponding to a special application, Since the operations are aligned by clock in most digital computing systems, a clock-based simulation system can hide most detailed implementation technology behind and make the system-level simulation tractable.","PeriodicalId":210565,"journal":{"name":"Workshop on VLSI Signal Processing","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115051571","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Vlsi Performance/precision Tradeoffs Of Approximate Rank-order Filters 近似秩序滤波器的Vlsi性能/精度权衡

Workshop on VLSI Signal Processing Pub Date : 1992-10-28 DOI: 10.1109/VLSISP.1992.641051

J. Narkiewicz, W. Burleson

引用次数: 3

The Exploitation Of Global Operations In Affine Space-time Mapping 仿射时空映射中全局运算的开发

Workshop on VLSI Signal Processing Pub Date : 1992-10-28 DOI: 10.1109/VLSISP.1992.641063

J. Rosseel, F. Catthoor, H. de Man

引用次数: 5

Qrd-based Square Root Free And Division Free Algorithms And Architectures 基于qrd的无平方根和无除法算法和架构

Workshop on VLSI Signal Processing Pub Date : 1992-10-28 DOI: 10.1109/VLSISP.1992.641077

K. Liu, E. Frantzeskakis

引用次数: 4

Real-time, Least-squares Adaptive Acoustic Beamforming: A Design Study. 实时、最小二乘自适应声波束形成:设计研究。

Workshop on VLSI Signal Processing Pub Date : 1992-10-28 DOI: 10.1109/VLSISP.1992.641076

I. Proudler

引用次数: 2

Optimizing Arithmetic Elements For Signal Processing 优化算法元素的信号处理

Workshop on VLSI Signal Processing Pub Date : 1992-10-28 DOI: 10.1109/VLSISP.1992.639176

T. K. Callaway, E. Swartzlander

引用次数: 51

High-speed Vlsi pipelined Processor Design For Lossless Image Data Compression 无损图像数据压缩的高速Vlsi流水线处理器设计

Workshop on VLSI Signal Processing Pub Date : 1992-10-28 DOI: 10.1109/VLSISP.1992.641054

W. Fang, B. Sheu

{"title":"High-speed Vlsi pipelined Processor Design For Lossless Image Data Compression","authors":"W. Fang, B. Sheu","doi":"10.1109/VLSISP.1992.641054","DOIUrl":"https://doi.org/10.1109/VLSISP.1992.641054","url":null,"abstract":"An efficient VLSI pipelined processor design for high-speed lossless compression based on \"Rice algorithm\" has been developed to meet the increasing strong demands on high-volumekigh-speed image data communication and storage. The Rice algorithm is an adaptive lossless coding scheme that provides near-optimal performance over a broad range of data entropies. The Rice algorithm is also an efficiently implementable scheme for VLSI realization. A VLSI pipelined architecture was developed to allow compact implementation of a single-chip VLSI compressor. This lossless compressor is named PSI14,K+ since it implements an advanced version of the Rice 's universal noiseless coding method called PSI14,K+. The chip layout was generated for a 1.0micron CMOS technology. It occupies a compact chip area of 5.1 x 5.3 mm2, with 49,000 transistors, 57 inpuvoutput pads, and 6 power/ground pads. The total power dissipation is 0.4 watts at the 40 MHz system clock with a 50% switching duty cycle. This compressor chip is mounted in a 68-pin pin-grid-array package. It can operate up to 40 Mpixelslsec. The potential applications of the proposed lossless compressor include database management systems, scientific instruments, CAE workstations, desktop computing machines, and the data systems that require highspeed compression without fidelity loss.","PeriodicalId":210565,"journal":{"name":"Workshop on VLSI Signal Processing","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125460058","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A New Algorithm For Order Statistic 一种新的序统计量算法

Workshop on VLSI Signal Processing Pub Date : 1992-10-28 DOI: 10.1109/VLSISP.1992.641081

B. K. Kar, D. Pradhan

{"title":"A New Algorithm For Order Statistic","authors":"B. K. Kar, D. Pradhan","doi":"10.1109/VLSISP.1992.641081","DOIUrl":"https://doi.org/10.1109/VLSISP.1992.641081","url":null,"abstract":"A new algorithm for rank filtering and stack filtering is presented here. This algorithm is simple and results in fast and easy implementations. It is based on transforming the given sequence into equivalent rank preserving sequences by means of bit manipulation. The algorithm can also implement stack filters without requiring threshold decomposition. INTRODUCTION Rank order filters(RF) [l] are nonlinear discrete time translation invariant filters. Ease of implementation has seen widespread use of these filters in speech and image processing. Used to determine the i-th order statistic of a set of n elements; i.e., i-th smallest element in a set, the minimum of a set of n elements for example corresponds to the first order statistic ( i = l), the maximum to the n-th order statistic (i = n). A median, therefore, corresponds to the n/2th order statistic or the “halfway point” of the set. Such bounds are used to suppress impulse noise, as well as to preserve edges, though using these bounds can complicate edge detection. Because of the success o f these filters, a new class of filters called stack filters[l4] has been developed, shown to form a large class of easily implementable nonlinear filters. The RF, as well as all compositions of morphological filters[2], are special cases of stack filters. This paper presents a new algorithm for rank order and stack filtering. based on transforming the given sequence into rank-preserving sequences shown to be less complex while yielding improved performance. A VLSI implementation of this filter has been reported in [20]. Organized into the following sections, this paper briefly reviews rank order and stack filters in Section 2. In Section 3, a new algorithm for rank order filtering is proposed with a modification of this algorithm which realizes stack filtering. Then, in Section 4, various methods of implementation of the proposed algorithms are described, where, the H-tree design of these filters is shown to be most area efficient. Finally, in Section 5, the complexity of the proposed scheme is discussed. through bit manipulation. The proposed rank order and stack filters are","PeriodicalId":210565,"journal":{"name":"Workshop on VLSI Signal Processing","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117145160","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Algebraic Recurrence Transformations For Massive Parallelism 大规模并行的代数递归变换

Workshop on VLSI Signal Processing Pub Date : 1992-10-28 DOI: 10.1109/VLSISP.1992.641065

Gerhard Fettweis, Lothar Thiele

引用次数: 10