High-speed Vlsi pipelined Processor Design For Lossless Image Data Compression

Abstract

An efficient VLSI pipelined processor design for high-speed lossless compression based on "Rice algorithm" has been developed to meet the increasing strong demands on high-volumekigh-speed image data communication and storage. The Rice algorithm is an adaptive lossless coding scheme that provides near-optimal performance over a broad range of data entropies. The Rice algorithm is also an efficiently implementable scheme for VLSI realization. A VLSI pipelined architecture was developed to allow compact implementation of a single-chip VLSI compressor. This lossless compressor is named PSI14,K+ since it implements an advanced version of the Rice 's universal noiseless coding method called PSI14,K+. The chip layout was generated for a 1.0micron CMOS technology. It occupies a compact chip area of 5.1 x 5.3 mm2, with 49,000 transistors, 57 inpuvoutput pads, and 6 power/ground pads. The total power dissipation is 0.4 watts at the 40 MHz system clock with a 50% switching duty cycle. This compressor chip is mounted in a 68-pin pin-grid-array package. It can operate up to 40 Mpixelslsec. The potential applications of the proposed lossless compressor include database management systems, scientific instruments, CAE workstations, desktop computing machines, and the data systems that require highspeed compression without fidelity loss.