Column Compression Multipliers For Signal Processing Applications

Abstract

An improved architecture for column-compression (CC) milltipliers is proposed; this architecture is targeted to applications in high performance signal processing. Constraints for column compression with full and half adders are analyzed, and, under these constraints, considerable flexibility for the realization of a new CC multiplier architecture is exposed. Using the example of an 8x8 bit CC multiplier, we show that this new architecture is more area efficient, and has shorter interconnections than the Dadda multiplier.