Proceedings of 1st International Symposium on Plasma Process-Induced Damage最新文献

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Role of Test Stress Levels in Detection of Process-Induced Latent Charging Damage in MOS Transistors 测试应力水平在MOS晶体管过程诱发潜在充电损伤检测中的作用
Proceedings of 1st International Symposium on Plasma Process-Induced Damage Pub Date : 1996-05-13 DOI: 10.1109/PPID.1996.715207
T. Broick, Lihua Peng, C. Viswanathan
{"title":"Role of Test Stress Levels in Detection of Process-Induced Latent Charging Damage in MOS Transistors","authors":"T. Broick, Lihua Peng, C. Viswanathan","doi":"10.1109/PPID.1996.715207","DOIUrl":"https://doi.org/10.1109/PPID.1996.715207","url":null,"abstract":"The role of stress level during constant-current Fowler-Nordheim stress test on degradation of device parameters is investigated. This effect is analyzed from the point of view of detection of plasma process-induced latent charging damage in submicron NMOS devices. It has been found that with increasing stress level the damage introduced by the test stress itself increases, mainly due to enhanced electron trap generation and interface deterioration. Under high stress levels used for assessment of charging damage, the effect of process-induced charging may be masked by the damage introduced during the test.","PeriodicalId":206175,"journal":{"name":"Proceedings of 1st International Symposium on Plasma Process-Induced Damage","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132563538","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Plasma Etching Induced Damage to Strained Si/SiGe/Si heterostructure 等离子体刻蚀对应变Si/SiGe/Si异质结构的损伤
Proceedings of 1st International Symposium on Plasma Process-Induced Damage Pub Date : 1996-05-13 DOI: 10.1109/PPID.1996.715221
P. K. Swain, D. Misra, M. Cole
{"title":"Plasma Etching Induced Damage to Strained Si/SiGe/Si heterostructure","authors":"P. K. Swain, D. Misra, M. Cole","doi":"10.1109/PPID.1996.715221","DOIUrl":"https://doi.org/10.1109/PPID.1996.715221","url":null,"abstract":"Dry etching can deteriously affect strained SiGe films by initiating misfit strain discontinuity in the film as well as in the interface. Annealing behavior of RIE induced defects is reported in this paper. Transmission electron microscopic investigations indicate creation of dislocation loops (having size in the range 10-14 A) due to ion bombardment stress. Deep Level Transient Spectroscopic measurements reveal defect levels at 0.62, 0.57, 0.56 and 0.44 eV for the dry etched samples annealed at 650, 700, 750 and 800 /spl deg/C respectively. Size of the dislocation loops estimated from the DLTS results are in good agreement with that obtained from the TEM measurements.","PeriodicalId":206175,"journal":{"name":"Proceedings of 1st International Symposium on Plasma Process-Induced Damage","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125354477","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Minimizing Mobile Ion Damage during the Ash Process 最小化灰烬过程中移动离子的伤害
Proceedings of 1st International Symposium on Plasma Process-Induced Damage Pub Date : 1996-05-13 DOI: 10.1109/PPID.1996.715218
J. Shi, S. Rounds, T. Noble, M. DeSarno, S. Fink, D. Shaner, H. Stants
{"title":"Minimizing Mobile Ion Damage during the Ash Process","authors":"J. Shi, S. Rounds, T. Noble, M. DeSarno, S. Fink, D. Shaner, H. Stants","doi":"10.1109/PPID.1996.715218","DOIUrl":"https://doi.org/10.1109/PPID.1996.715218","url":null,"abstract":"It is generally accepted that mobile ion contamination and the subsequent device damage is a function of the amount of positively charged ions in the ash gas. As device dimensions shrink and gate dielectric thicknesses decrease, the potential for device damage at the photoresist strip level increases. Ozone ashing traditionally has been known to have extremely low ion concentrations in the gas, while barrel, radio frequency, and downstream microwave ashers have posed more damage issues. At the same time, implant and etch conditions frequently make resist harder (or with a carbonized top layer) and resist removal becomes more difficult without device damage. Fusion has developed a downstream microwave asher that produces extremely low ion concentrations while still maintaining excellent ash rates for different applications. Data from the Fusion asher is compared with commercially available ozone and plasma systems under a variety of temperature and RF power conditions. MOS device wafers were used as the primary method of testing mobile ion damage. The mobile ion results of wafers ashed with the Fusion downstream plasma asher are superior to those of wafers ashed with other plasma ashing systems and are comparable to those obtained when resist is removed by ozone asher or conventional wet stripping methods.","PeriodicalId":206175,"journal":{"name":"Proceedings of 1st International Symposium on Plasma Process-Induced Damage","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129739215","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Quantifying Wafer Charging During Via Etch 经孔蚀刻过程中晶圆充电的定量研究
Proceedings of 1st International Symposium on Plasma Process-Induced Damage Pub Date : 1996-05-13 DOI: 10.1109/PPID.1996.715196
W. Lukaszek, A. Birrell
{"title":"Quantifying Wafer Charging During Via Etch","authors":"W. Lukaszek, A. Birrell","doi":"10.1109/PPID.1996.715196","DOIUrl":"https://doi.org/10.1109/PPID.1996.715196","url":null,"abstract":"A CHARM/sup TM/-2 investigation of wafer charging during via etching shows that wafer surface conditions strongly influence the observed results. Under identical process conditions, bare wafers underestimate the charging results. When wafers are covered with patterned resist, much higher surface-substrate potentials and current densities are observed.","PeriodicalId":206175,"journal":{"name":"Proceedings of 1st International Symposium on Plasma Process-Induced Damage","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128432558","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
The Degradation of MOS Devices by Source/Drain Ion Impantation 源极/漏极离子注入对MOS器件的降解
Proceedings of 1st International Symposium on Plasma Process-Induced Damage Pub Date : 1996-05-13 DOI: 10.1109/PPID.1996.715240
Sang-Don Lee, J. Son, Jaeseog Yoon, K. Huh, Dooyoung Yang
{"title":"The Degradation of MOS Devices by Source/Drain Ion Impantation","authors":"Sang-Don Lee, J. Son, Jaeseog Yoon, K. Huh, Dooyoung Yang","doi":"10.1109/PPID.1996.715240","DOIUrl":"https://doi.org/10.1109/PPID.1996.715240","url":null,"abstract":"In this paper, we have evaluated the effect of n/sup +/-As S/D implantation on the performance of MOS capacitor and transistor. The BVdss values of n- MOSFETs, implanted with the higher dose(=5xI0/sup 15/) and energy(=40KeV) ions of As, were observed to be dependent on the channel length due to larger GIDL current. With increasing the channel length of n- MOSFET, the BVdss value was observed to be lower due to the GIDL current increased by band-to-defect tunneling. Also, the capacitors implanted with the higher dose and energy ions of As showed worse TDDB properties and larger hole trapping, than those implanted with the lower dose(=1x10/sup 15/) and energy(=30KeV).","PeriodicalId":206175,"journal":{"name":"Proceedings of 1st International Symposium on Plasma Process-Induced Damage","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128850032","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Application of Plasma Charging Probe to Production HDP CVD Tool 等离子体充电探头在生产HDP CVD刀具中的应用
Proceedings of 1st International Symposium on Plasma Process-Induced Damage Pub Date : 1996-05-13 DOI: 10.1109/PPID.1996.715205
G. Roche, J. Mcvittie
{"title":"Application of Plasma Charging Probe to Production HDP CVD Tool","authors":"G. Roche, J. Mcvittie","doi":"10.1109/PPID.1996.715205","DOIUrl":"https://doi.org/10.1109/PPID.1996.715205","url":null,"abstract":"Measurements of plasma induced voltage (V/sub c/) are performed real time using an in situ probe. The probe was installed on a Deep Sub Micron (DSM) 9900 CVD tool from Lam Research Corporation. The data was collected and modeled using Response Surface Modeling (RSM). A process parameter space of low V/sub c/ was identified.","PeriodicalId":206175,"journal":{"name":"Proceedings of 1st International Symposium on Plasma Process-Induced Damage","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115835744","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Effect of Process & Etch Variables on Contact Resistance 工艺和蚀刻变量对接触电阻的影响
Proceedings of 1st International Symposium on Plasma Process-Induced Damage Pub Date : 1996-05-13 DOI: 10.1109/PPID.1996.715223
A. Macphie, P. Anderson, G. Boyd
{"title":"Effect of Process & Etch Variables on Contact Resistance","authors":"A. Macphie, P. Anderson, G. Boyd","doi":"10.1109/PPID.1996.715223","DOIUrl":"https://doi.org/10.1109/PPID.1996.715223","url":null,"abstract":"Contact resistance can be influenced by a number of different parameters including autodoping of the underlying substrate from dielectric films, incomplete removal of damaged Silicon, etch depth into the underlying substrate and subsequent contact area with the diffused region. Evaluation of the effect of different etch chemistries, etch times and resist strip chemistries on the contact resistances of a number of processes took place. The effect of each of the variables is quantified from the experimental results and an explanation for the behaviour proposed.","PeriodicalId":206175,"journal":{"name":"Proceedings of 1st International Symposium on Plasma Process-Induced Damage","volume":"108 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122676699","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Analytical Circuit Model Approach to Charging Damage in Plasma/implantation Processing 等离子体/注入过程中充电损伤的分析电路模型方法
Proceedings of 1st International Symposium on Plasma Process-Induced Damage Pub Date : 1996-05-13 DOI: 10.1109/PPID.1996.715206
W. En, B.P. Shich, N. Cheung
{"title":"Analytical Circuit Model Approach to Charging Damage in Plasma/implantation Processing","authors":"W. En, B.P. Shich, N. Cheung","doi":"10.1109/PPID.1996.715206","DOIUrl":"https://doi.org/10.1109/PPID.1996.715206","url":null,"abstract":"Through the use of an analytical circuit model approach, the simulation can identify the phase- space of plasma, device, and bias conditions that can minimize or eliminate charging damage and still maintain high throughput. The simulation determines the interactions between the charging currents, device structure and substrate bias to determine the physical interactions between the charging currents and device structure. This approach has been applied to Plasma Immersion Ion Implantation (PIII). Using the simulator, short pulse widths around 1/spl mu/s allow the highest throughput with negligible damage, and repetition rates on the order of several kHz is optimal for microsecond pulses. Experimental and simulation results show that high dose rates of - 1014/sec can be achieved with negligible damage.","PeriodicalId":206175,"journal":{"name":"Proceedings of 1st International Symposium on Plasma Process-Induced Damage","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131875757","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Plasma-induced Oxide Contamination In a 0.35 /spl mu/m CMOS Process 0.35 /spl μ m CMOS工艺中等离子体诱导的氧化物污染
Proceedings of 1st International Symposium on Plasma Process-Induced Damage Pub Date : 1996-05-13 DOI: 10.1109/PPID.1996.715244
M. Karnett, J. Zhou, S. Ghosh, D. Echtle, L. Fritz, K. Wu
{"title":"Plasma-induced Oxide Contamination In a 0.35 /spl mu/m CMOS Process","authors":"M. Karnett, J. Zhou, S. Ghosh, D. Echtle, L. Fritz, K. Wu","doi":"10.1109/PPID.1996.715244","DOIUrl":"https://doi.org/10.1109/PPID.1996.715244","url":null,"abstract":"Plasma contamination in a 0.35/spl mu/m triple-level metal CMOS process was investigated as a function of asher type and processing chamber. Electrical PMOS transistor performance as well as physical and electrical gate oxide thickness were significantly degraded upon exposure of a sacrificial oxide to a plasma ash following a masked, P-Channel threshold adjust ion implant. The contamination was isolated to a specific asher, found to be radial in nature across a wafer, and consistently worse in one of the two chambers used during the ash process. The contamination dramatically reduced the wet etch rate of the sacrificial oxide, leading to incomplete removal prior to gate oxide growth. Increasing the wet strip time of the sacrificial oxide improved the ability to remove this contaminated film, but was limited by minimal field oxide thickness requirements to avoid field inversion. Transferring the ash process to an alternative, low-damage, down-stream asher eliminated the plasma contamination.","PeriodicalId":206175,"journal":{"name":"Proceedings of 1st International Symposium on Plasma Process-Induced Damage","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133998208","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Inductive Damage and the Impact of RF Power and Magnetic Field During MERIE Processes 微波过程中射频功率和磁场的感应损伤及影响
Proceedings of 1st International Symposium on Plasma Process-Induced Damage Pub Date : 1996-05-13 DOI: 10.1109/PPID.1996.715220
A. Salah, O. Awadelkarim, Y. Chan, J. Werking
{"title":"Inductive Damage and the Impact of RF Power and Magnetic Field During MERIE Processes","authors":"A. Salah, O. Awadelkarim, Y. Chan, J. Werking","doi":"10.1109/PPID.1996.715220","DOIUrl":"https://doi.org/10.1109/PPID.1996.715220","url":null,"abstract":"We report on a new form of process-induced damage to submicron MOS transistors caused by metal 1 plasma etching. This form of damage, herein referred to as \"inductive damage\", is suggested to arise from inductive coupling between interconnect circuitry and time-varying magnetic fields during plasma exposure. We demonstrate the occurrence of inductive damage through the use of specially designed test structures consisting of fuse-attached metal loops acting as inductive antennas and connecting the gate and substrate of n-channel and p-channel MOSFETs (Fig. 1). The MOSFETs, with lightly doped drains and channel lengths of 0.25 pm and 0.50 pm, are fabricated on 200 mm p/p'silicon wafers using a full CMOS process flow. The metal 1 etch step was carried out using a BC1JN2/Cl2 plasma in a magnetically-enhanced reactive ion etching (MERIE) tool. From our results, the presence of inductive damage in NMOS transistors is unambiguously established. This is exemplified in the results for maximum transconductance (gm) and subthreshold swing (S) shown in Figs. 2 and 3, respectively. These figures clearly show degradations in both gm and S when devices with inductive antennas are compared to reference devices. We observe that inductive damage is seemingly absent in PMOS devices. We also show that inductive damage in NMOS devices is influenced by the rf power during metal 1 overetch; inductive damage in the transistor increases with increasing r f power (Fig. 4). However, magnetic field intensity (B) in the metal 1 MERIE process is seen to have little effect on inductive damage.","PeriodicalId":206175,"journal":{"name":"Proceedings of 1st International Symposium on Plasma Process-Induced Damage","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126629748","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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