{"title":"The Effect of Guard Line on Plasma Damage","authors":"Yeon-Cheol Heo, Byung-Gook Park, J. Lee","doi":"10.1109/PPID.1996.715211","DOIUrl":"https://doi.org/10.1109/PPID.1996.715211","url":null,"abstract":"The effective overetch time, the elapsed time after pattern seperation, determines the level of damage, because the plasma damage induced during metal etch process depends on the overetch time and only weakest pattem is damaged during process if patterns are connected. For the reduction of the effective overetch time, the narrow distribution of spacings between patterns are required, because the etch rate depends on the width of spacing and the lowest etch rate determines the total etch time and/or the effective overetch time. We have designed the dummy pattern i.e. guard line pattern for the narrow distribution of spacings. The level of damage depends on the connection configuration of outer pattern i.e. guard line pattern. The antenna patterns with floating guard line reveal less damage than the patterns with guard line connected to substrate and a simple floating guard line formation technology is proposed without increasing design complexity.","PeriodicalId":206175,"journal":{"name":"Proceedings of 1st International Symposium on Plasma Process-Induced Damage","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133830189","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
T. Broick, V. Prabhakar, J. Werking, Y. Chan, C. Viswanathan
{"title":"Oxide modification near gate edges due to plasma etching of poly-Si gate in submicron MOSFET","authors":"T. Broick, V. Prabhakar, J. Werking, Y. Chan, C. Viswanathan","doi":"10.1109/PPID.1996.715232","DOIUrl":"https://doi.org/10.1109/PPID.1996.715232","url":null,"abstract":"The paper discusses the performance of submicron transistors from the point of view of damage introduced at the device gate edge by plasma etching. Electrical results, indicating a difference in the gate oxide thickness under the gate edge between devices processed with different plasma tools are confirmed by TEM measurements. It is concluded, that chlorine residue of plasma environment origin, incorporated in the structure at the gate edges, enhances oxide growth in this region during poly reoxidation step and affects the interface quality over the gate/LDD overlap.","PeriodicalId":206175,"journal":{"name":"Proceedings of 1st International Symposium on Plasma Process-Induced Damage","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129396008","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A Comparison Of Hot-electron And Fowler-nordheim Characterization Of Charging Events In A 0.5-/spl mu/m Cmos Technology","authors":"T. Hook, K. Watson, S. Mittl, C. Johnson","doi":"10.1109/PPID.1996.715229","DOIUrl":"https://doi.org/10.1109/PPID.1996.715229","url":null,"abstract":"A comparison of techniques used to expose latent damage resulting from process-induced charging events is presented. In particular, the result of hot- electron stress is compared to Fowler-Nordheim stress for three different charging signatures. Although both techniques can illuminate some charging events, hot-carrier stressing is shown to be superior because it is sensitive to all three types of charging events, and can quantify the effect of these process-induced events.","PeriodicalId":206175,"journal":{"name":"Proceedings of 1st International Symposium on Plasma Process-Induced Damage","volume":"504 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132454073","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
H. Denton, G. Grynkewich, V. Ilderem, F. Lin, P. Parris, H. Shin
{"title":"Process-Induced Charge Damage in PETEOS for Interlevel Dielectric Applications","authors":"H. Denton, G. Grynkewich, V. Ilderem, F. Lin, P. Parris, H. Shin","doi":"10.1109/PPID.1996.715214","DOIUrl":"https://doi.org/10.1109/PPID.1996.715214","url":null,"abstract":"This paper reports on the process characterization and optimization to reduce process-induced damage by PETEOS deposition used for interlevel dielectric applications. It is shown that the deposition-etch- deposition PETEOS process utilized to fill the narrow gaps between metal spaces has a major impact on the electrical parameters. Elimination of the magnetic field and increasing the pressure in the \"etch\" portion of this process could significantly reduce charging.","PeriodicalId":206175,"journal":{"name":"Proceedings of 1st International Symposium on Plasma Process-Induced Damage","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128547079","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Thin-Oxide Charging Damage to Microelectronic Test Structures in an Electron-Cyclotron-Resonance Plasma","authors":"J. Friedmann, J. Shohet, J. P. Mcvitie, S. Ma","doi":"10.1109/PPID.1996.715235","DOIUrl":"https://doi.org/10.1109/PPID.1996.715235","url":null,"abstract":"Processing yields in electron‐cyclotron‐resonance (ECR) and other high‐density plasma sources will be increasingly limited by plasma‐induced damage. This work investigates the effects of plasma nonuniformities on charging damage to polysilicon‐gate MOS capacitor test structures exposed to O2 ECR plasmas. The nonuniformities were produced by independently biasing electrodes located above the wafer. The damage was characterized with ramp‐voltage breakdown measurements. Comparison of calculated profiles of the potential difference across the gate‐oxide layers of the MOS capacitors with whole wafer maps of the breakdown voltage measurements shows that maximum damage occurs where the oxide potential difference is largest but only in the presence of plasma nonuniformities.","PeriodicalId":206175,"journal":{"name":"Proceedings of 1st International Symposium on Plasma Process-Induced Damage","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130932877","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Non-destructive Prognosis Method Of Oxide Degradation- A Rapid Monitoring Of Oxide Energy Band Changes Cause By Semiconductor Processing","authors":"P. K. Aum, T. Dao","doi":"10.1109/PPID.1996.715193","DOIUrl":"https://doi.org/10.1109/PPID.1996.715193","url":null,"abstract":"A new non-destructive method is proposed to characterize the gate insulator quality and degradation mechanism. In this method, a new parameter called \"Protection Voltage\", is extracted during Fowler-Nordheim (FN) stress on the gate insulator. By using capactor devices of 6nm thermal gate oxide on silicon substrate, this work found six useful characteristics of the \"Protection Voltage\" in oxide wearout measurements and understanding oxide energy band degradation mechanisms.","PeriodicalId":206175,"journal":{"name":"Proceedings of 1st International Symposium on Plasma Process-Induced Damage","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127333434","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}