{"title":"A VLSI Architecture for Anti-Aliasing","authors":"C. Romanova, U. Wagner","doi":"10.2312/EGGH/EGGH89/075-090","DOIUrl":"https://doi.org/10.2312/EGGH/EGGH89/075-090","url":null,"abstract":"Computer-synthesized images exhibit the typical artifacts of raster displays, called alias ing, rastering, staircasing or the \"jaggies\". Display of an image on a raster CRT requires the sampling the two dimensional image signal I( x, y) to obtain a pixel-based description of intensity. Unfortinately, this sampling process treates the pixel as a mathematical point and the point sampling of an unfiltered object is never correct at any resolution. Aliasing effects (spatial and temporal) are due to undersampling of the image signal. Spatial aliasing occurs when images contain frequencies greater than one half the spa tial sampling frequency. Lines that should be straight appear jagged, very small objects may not be visible, portions of long thin objects may disappear.","PeriodicalId":206166,"journal":{"name":"Advances in Computer Graphics Hardware","volume":"272 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115019866","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Partially Ordered Search Indices in the Organization of a Fixed Hierarchy","authors":"J. Skyttä, T. Takala","doi":"10.2312/EGGH/EGGH87/039-046","DOIUrl":"https://doi.org/10.2312/EGGH/EGGH87/039-046","url":null,"abstract":"The mapping of even very advanced algorithms directly to hardware does not typically bring good results as these algorithms are originally designed for sequential processing. However, the power of the modern integration technology lies in its ability to produce high volumes of reasonably complex elements at moderate cost. For utilization of these possibilities the algorithms and data structures already developed must be redesigned for parallel computation.","PeriodicalId":206166,"journal":{"name":"Advances in Computer Graphics Hardware","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130817896","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"PS: Polygon Streams - A Distributed Architecture for Incremental Computation Applied to Graphics","authors":"Rajiv Gupta","doi":"10.2312/EGGH/EGGH89/091-111","DOIUrl":"https://doi.org/10.2312/EGGH/EGGH89/091-111","url":null,"abstract":"Polygon Streams is a distributed system with multiple processors and strictly local communication. A unique custom VLSI chip that constitutes an independent processing module forms a stage of the PS pipeline. The number of these modules in PS is a variable that is determined by the application. PS features a modular architecture, multi-ported on-chip memory, bit-serial arithmetic, and a pipeline whose computation can be dynamically configured. The PS design closely subscribes to the system characteristics favored by VLSI. \u0000 \u0000The task of scan conversion for rendering computer graphics images on raster scan displays is very intensive in computation and pixel information access. It is very coherent and suitable, however, for forward difference algorithms. The discrete and regular layout of the raster display, in conjunction with the largely local effect of a pixel on an image, make rendering amenable to parallel architectures with localized memory and communication. These are precisely the attributes favored by VLSI and typical of PS. \u0000 \u0000A modification of the Digital Differential Analyzer (DDA) is implemented to Gouraud Shade and depth buffer convex polygons at high speeds. The scan conversion task is distributed over the processors to efficiently subdivide the image space and maximize concurrency of processor operation. \u0000 \u0000A study of the tradeoffs and architectural choices of the PS reveal the merits and deficits of the PS approach in comparison with Pixel-Planes, SLAMs, Super-Buffers, and SAGE.","PeriodicalId":206166,"journal":{"name":"Advances in Computer Graphics Hardware","volume":"28 11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134144691","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
G. Vaudin, G. Nudd, T. Atherton, S. Clippingdale, N. Francis, R. Howarth, D. Kerbyson, R. A. Packwood, D. Walton
{"title":"A Generalised Parallel Architecture for Image Based Algorithms","authors":"G. Vaudin, G. Nudd, T. Atherton, S. Clippingdale, N. Francis, R. Howarth, D. Kerbyson, R. A. Packwood, D. Walton","doi":"10.2312/EGGH/EGGH89/113-132","DOIUrl":"https://doi.org/10.2312/EGGH/EGGH89/113-132","url":null,"abstract":"Real time image generation and image understanding require levels of computing power, that are beyond that available from conventional sequential machines. Current commercially available systems aimed at this area make use of special purpose hardware to achieve the necessary throughput, but these systems can only achieve their performance for a restricted set of algorithms that are implemented in the hardware. A programmable general purpose parallel machine offers the possibility to achieve the required performance without restricting the choice of algorithm. Unfortunately it is by no means clear which parallel architecture should be used. Many general purpose parallel architectures have been proposed but none has proved universally applicable, their problem being that their performance tends to be highly dependent on the algorithms that are being used, and it is therefore difficult to claim any of them are truly general purpose. However parallel machines can still be highly effective in specific problem areas where the class of algorithm is known. Our aim has been to design a parallel machine that is optimised for image based algorithms in both graphics and image understanding. The architecture is not limited to a specific set of algorithms, but is instead optimised towards a class of algorithms which we believe are representative of image based algorithms. This has not been a paper study, but has resulted in us implementing such an architecture. We have achieved this by making use of industry standard components and integrating them into a system level architectural design. Also we have where possible used industry standard programming languages to program our machine.","PeriodicalId":206166,"journal":{"name":"Advances in Computer Graphics Hardware","volume":"05 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130339138","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Point-driven Generation of Images from a Hierarchical Data Structure","authors":"Dirk de Jong, P. Slobbe, M. V. Splunter","doi":"10.2312/EGGH/EGGH88/027-039","DOIUrl":"https://doi.org/10.2312/EGGH/EGGH88/027-039","url":null,"abstract":"In this paper, a system is described which renders an image from a hierarchical data structure in a point-driven way. The data structure allows dynamic color mapping and arbitrary affine transformations of objects with respect to their parent coordinate system. The point driven method allows for easy VLSI implementation, efficient use oj memory and exploitation of parallelism.","PeriodicalId":206166,"journal":{"name":"Advances in Computer Graphics Hardware","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122516632","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Two-level Pipelining of Systolic Array Graphics Engines","authors":"J. Jayasinghe, O. E. Herrmann","doi":"10.2312/EGGH/EGGH89/133-148","DOIUrl":"https://doi.org/10.2312/EGGH/EGGH89/133-148","url":null,"abstract":"In a systolic array, the maximum operating speed is determined by the most complex operation performed. In a systolic army graphics engine, capable of generating high quality images, one has to perform complex operations at a very high speed. We propose to use pipelined functional units in systolic army graphics engines as they can perform complex operations at high speeds. Due to time-varying discontinuities of operations performed by systolic army graphics engines, introduction of pipelined functional units is a complex problem. In this paper we present a methodology which solves this problem by a graphtheoretic approach. Furthermore, we characttTize the architectures which can be improved by pipelined functional units.","PeriodicalId":206166,"journal":{"name":"Advances in Computer Graphics Hardware","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115833786","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"The HERO Algorithm for Ray-Tracing Octrees","authors":"M. Agate, R. L. Grimsdale, P. Lister","doi":"10.2312/EGGH/EGGH89/061-073","DOIUrl":"https://doi.org/10.2312/EGGH/EGGH89/061-073","url":null,"abstract":"An algorithm is presented for rapid traversal of octree data structures, in order to enhance the speed of ray tracing for scenes of high complexity. At each level of the octree, the algorithm generates the addresses of child voxels in the order they are penetrated by the ray. This requires only a few arithmetic operations and simple logical operations. A depth-first search of the tree is used to yield the first terminal voxel hit by the ray, thus hidden objects are not processed. The algorithm is designed specifically for implementation as HERO: A Hardware Enhancer for Ray-tracing Octrees.","PeriodicalId":206166,"journal":{"name":"Advances in Computer Graphics Hardware","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116903685","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A Two-Dimensional Frame Buffer Processor","authors":"A. Kaufman","doi":"10.2312/EGGH/EGGH87/093-109","DOIUrl":"https://doi.org/10.2312/EGGH/EGGH87/093-109","url":null,"abstract":"The two-dimensional Frame Buffer Processor (FBP) is part of a proposed raster graphics computer architecture. It is a hardware-oriented organisation of a variation of a bitblt engine with a much richer repertoire. In addition, the FBP gives support to window management, transformations, and assists in some image operations ordinarily performed in software. The introduction of the FBP as a co-processor to geometry and video processors would increase efficiency and speed of graphics systems and bitmap workstations. A special skewed frame-buffer organisation, which allows parallel memory access, further improves system performance.","PeriodicalId":206166,"journal":{"name":"Advances in Computer Graphics Hardware","volume":"255 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124199159","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Viewing and Rendering Processor for a Volume Visualization System","authors":"A. Kaufman, R. Bakalash, D. Cohen-Or","doi":"10.2312/EGGH/EGGH89/171-178","DOIUrl":"https://doi.org/10.2312/EGGH/EGGH89/171-178","url":null,"abstract":"The architecture and the hardware realization of the 3D Viewing and Rendering Processor is presented. This processor is a component of the Cube architecture, developed primarily for volume visualization. The processor generates 2D shaded orthographic, parallel, and perspective projections of the volumetric image of n3 voxels in O(n2log n) time. This performance is attributed to a unique skewed memory organization, a special ray projection bus, an extended viewing architecture, and a new congradient shading technique. A reduced-resolution prototype has been realized in hardware using printed circuit board technology and has been running in true real time. Currently, a VLSI version of the prototype is being tested.","PeriodicalId":206166,"journal":{"name":"Advances in Computer Graphics Hardware","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121318308","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Accurate Scanconversion of Triangulated Surfaces","authors":"J. Rossignac","doi":"10.2312/EGGH/EGGH91/116-137","DOIUrl":"https://doi.org/10.2312/EGGH/EGGH91/116-137","url":null,"abstract":"Scanconverting a planar face produces depth-values for pixels totally or partly covered by the projection of that face. State-of-the-art hardwaresupported scan conversion techniques use sub pixel adjustment and extended precision calculations to achieve an acceptable depth-accuracy despite numeric round-off errors. Unfortunately, this depth-accuracy only holds for the interior pixels of the face. During the scanconversion of the boundaries of polyhedral solids or of the tesselations of curved surfaces, significantly larger depth-errors may occur at pixels traversed by the projection of the bounding edges. These errors are due to the use of the wrong surface equations resulting from an erroneous classification of pixels with respect to the projections of faces. They may lead to logical mistakes of serious consequences for hidden-surface removal and for solid-modeling applications. To address this problem, a new scanconversion technique is presented, which exploits surface data and face/face adjacency information to infer face-projections. For simplicity, the exposition is confined to triangular faces of manifolds, where each edge is adjacent to two triangles. At pixels covered by the projection of an edge, the surface depth computed in the standard manner is compared to the depth of the surface supporting the adjacent triangle. Pixel classification is obtained by taking into account the result of this comparison and the orientations of both faces.","PeriodicalId":206166,"journal":{"name":"Advances in Computer Graphics Hardware","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127359090","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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