一种用于抗混叠的VLSI架构

C. Romanova, U. Wagner
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引用次数: 6

摘要

计算机合成的图像呈现出栅格显示的典型伪影,称为混叠、栅格、阶梯或锯齿。在光栅CRT上显示图像需要对二维图像信号I(x, y)进行采样,以获得基于像素的强度描述。不幸的是,这种采样过程将像素视为一个数学点,在任何分辨率下,对未过滤对象的点采样都是不正确的。混叠效应(空间和时间)是由于图像信号的欠采样。当图像包含的频率大于采样频率的一半时,就会发生空间混叠。应该笔直的线条看起来参差不齐,非常小的物体可能不可见,长而细的物体的部分可能会消失。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A VLSI Architecture for Anti-Aliasing
Computer-synthesized images exhibit the typical artifacts of raster displays, called alias­ ing, rastering, staircasing or the "jaggies". Display of an image on a raster CRT requires the sampling the two dimensional image signal I( x, y) to obtain a pixel-based description of intensity. Unfortinately, this sampling process treates the pixel as a mathematical point and the point sampling of an unfiltered object is never correct at any resolution. Aliasing effects (spatial and temporal) are due to undersampling of the image signal. Spatial aliasing occurs when images contain frequencies greater than one half the spa­ tial sampling frequency. Lines that should be straight appear jagged, very small objects may not be visible, portions of long thin objects may disappear.
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