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Advances in Computer Graphics Hardware最新文献

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A Virtual Memory System Organization for Bit-Mapped Graphics Displays 位图图形显示的虚拟内存系统组织
Advances in Computer Graphics Hardware Pub Date : 1900-01-01 DOI: 10.2312/EGGH/EGGH89/199-212
A. C. Barkans
{"title":"A Virtual Memory System Organization for Bit-Mapped Graphics Displays","authors":"A. C. Barkans","doi":"10.2312/EGGH/EGGH89/199-212","DOIUrl":"https://doi.org/10.2312/EGGH/EGGH89/199-212","url":null,"abstract":"Described is a display sub-system, designed for support of a very high speed rendering engine. It provides high-performance graphics to an environment that consists of a hierarchy of resizable windows. The concept of virtual memory has been applied with the organization of the virtual to physical address spaces having a unique mapping that fits the organization of a bit-mapped graphics memory display.","PeriodicalId":206166,"journal":{"name":"Advances in Computer Graphics Hardware","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128660077","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
The Graphics Unit of the INTEL I80860 INTEL I80860的图形单元
Advances in Computer Graphics Hardware Pub Date : 1900-01-01 DOI: 10.2312/EGGH/EGGH89/229-247
U. Kursawe
{"title":"The Graphics Unit of the INTEL I80860","authors":"U. Kursawe","doi":"10.2312/EGGH/EGGH89/229-247","DOIUrl":"https://doi.org/10.2312/EGGH/EGGH89/229-247","url":null,"abstract":"The Intel 180860 is a very powerful RISC processor, designed for applications that require a large amount of floating point and integer calculations. Additionally it supports graphics applications with a Graphics hardware unit. The aim of this article is to investigate, for which application this unit is useful and whether the results obtained by the help of this unit are better as with standard C or assembly implementations of the same algorithm.","PeriodicalId":206166,"journal":{"name":"Advances in Computer Graphics Hardware","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123112636","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An Integrated Highly Parallel Architecture for Image Reconstruction 一种集成的高度并行图像重建体系结构
Advances in Computer Graphics Hardware Pub Date : 1900-01-01 DOI: 10.2312/EGGH/EGGH88/053-064
D. Lattard, G. Mazaré
{"title":"An Integrated Highly Parallel Architecture for Image Reconstruction","authors":"D. Lattard, G. Mazaré","doi":"10.2312/EGGH/EGGH88/053-064","DOIUrl":"https://doi.org/10.2312/EGGH/EGGH88/053-064","url":null,"abstract":"The large amount of information and computations is a critical problem in image processing. In this paper we show a highly parallel method to do image reconstruction which performs at real-time, using an asynchronous cellular array. The highly parallel architecture we propose is novel, its main cnaracteristic is the message communication mechanism based upon message routing and mailbox principles. \u0000 \u0000After introducing the image reconstruction problem, we present the main reconstruction techniques and the sequential algorithms. We explain how to process these algorithms on a network. We describe this new integrated parallel architecture, its originalities and the system performing the whole reconstruction. We present the efficiency of this parallel image reconstruction method and the performance of the network.","PeriodicalId":206166,"journal":{"name":"Advances in Computer Graphics Hardware","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115558521","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An Exact Incremental Hidden Surface Removal Algorithm 一种精确增量隐面去除算法
Advances in Computer Graphics Hardware Pub Date : 1900-01-01 DOI: 10.2312/EGGH/EGGH87/021-037
A. Kuijk, P. Hagen, Varol Akman
{"title":"An Exact Incremental Hidden Surface Removal Algorithm","authors":"A. Kuijk, P. Hagen, Varol Akman","doi":"10.2312/EGGH/EGGH87/021-037","DOIUrl":"https://doi.org/10.2312/EGGH/EGGH87/021-037","url":null,"abstract":"This paper describes an incremental Hidden Surface Removal Algorithm (HSRA), developed to be embedded in a new architecture for raster graphics described in [1,7]. The algorithm can be classified as \"exact\" since it operates in object space, rather than image space. It can be classified as \"incremental\" because this HSRA is able to support addition, removal and changes on a single object or a group of objects. Thus a firm basis for powerful interaction and animation is established. Due to specially designed data structures for both geometric objects as well as storage of these objects, the hidden surface removal calculation on a complete scene will have the same time complexity as existing algorithms. However, the effort needed for incremental changes is much less than any other known algorithm. The data structures as well as the algorithm are designed to exploit parallelism in computation.","PeriodicalId":206166,"journal":{"name":"Advances in Computer Graphics Hardware","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116875498","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Towards a Taxonomy for Display Processors 迈向显示处理器的分类法
Advances in Computer Graphics Hardware Pub Date : 1900-01-01 DOI: 10.2312/EGGH/EGGH89/003-036
Bengt-Olaf Schneider
{"title":"Towards a Taxonomy for Display Processors","authors":"Bengt-Olaf Schneider","doi":"10.2312/EGGH/EGGH89/003-036","DOIUrl":"https://doi.org/10.2312/EGGH/EGGH89/003-036","url":null,"abstract":"Image generation for raster displays proceeds in two main steps: geometry processing and pixel processing. The snbsystem performing the pixel processing is called display processor. \u0000 \u0000In the paper a model for the display processor is developed that takes into account both function and timing properties. The model identifies scan conversion, hidden surface removal, shading and anti-aliasing as tile key functions of the display processor. The timing model is expressed in an in equation being fundamental for all display processor architectures. \u0000 \u0000On the basis of that model a taxonomy is presented which classifies display processors according to four main criteria: function, partitioning, architecture and performance. \u0000 \u0000The taxonomy is applied to five real display processors: Pixel-planes, SLAM, PROOF, the Ray-Casting Machine and the Structured Frame Store System. \u0000 \u0000Investigation of existing display processor architectures on the basis of the developed taxonomy revealed a potential new architecture. This architecture partitions the image generation process in image space and employs a tree topology.","PeriodicalId":206166,"journal":{"name":"Advances in Computer Graphics Hardware","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125752590","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A Hardware Algorithm for Fast Realistic Image Synthesis 一种快速真实感图像合成的硬件算法
Advances in Computer Graphics Hardware Pub Date : 1900-01-01 DOI: 10.2312/EGGH/EGGH89/037-060
A. Yilmaz, S. Hagestein, E. Deprettere, P. Dewilde
{"title":"A Hardware Algorithm for Fast Realistic Image Synthesis","authors":"A. Yilmaz, S. Hagestein, E. Deprettere, P. Dewilde","doi":"10.2312/EGGH/EGGH89/037-060","DOIUrl":"https://doi.org/10.2312/EGGH/EGGH89/037-060","url":null,"abstract":"A VLSI oriented algorithm, for the implementation of a generalized two-pass radiosity method is presented. The method allows any reflection behavior, varying from purely diffuse to perfect mirroring. Moreover, objects may be defined in terms of curved (Bezier) surfaces. All computations in the preand postprocess are similar and ray-tracing based, consequently a single architecture can be devised for both passes. This architecture, when built on ray-rotating and ray-tracing pipelined processors such as Cordics, results in a very high throughput VLSI implementation of the proposed generalized two-pass procedure.","PeriodicalId":206166,"journal":{"name":"Advances in Computer Graphics Hardware","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116204195","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A Survey of Simulator Requirements 模拟器需求调查
Advances in Computer Graphics Hardware Pub Date : 1900-01-01 DOI: 10.2312/EGGH/EGGH86/041-044
Hans Joseph
{"title":"A Survey of Simulator Requirements","authors":"Hans Joseph","doi":"10.2312/EGGH/EGGH86/041-044","DOIUrl":"https://doi.org/10.2312/EGGH/EGGH86/041-044","url":null,"abstract":"Simulators have been developed to train pilots, sailors or car drivers withoutthe costs and risks of moving their real vehicles. To obtain high success intraining, the simulators have to provide a high level of realism. Therequirements of simulators and their CIG-system, especially the 'real time'requirement, result from this need for realism. 'Real time' means, the systemhas to react in less than 150 ms after the trainnee has made an input.","PeriodicalId":206166,"journal":{"name":"Advances in Computer Graphics Hardware","volume":"100 10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125970162","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Distributed Frame Buffer within a Window-Oriented High Performance Graphics System 面向窗口的高性能图形系统中的分布式帧缓冲区
Advances in Computer Graphics Hardware Pub Date : 1900-01-01 DOI: 10.2312/EGGH/EGGH89/261-274
T. Haaker, H. Selzer, Hans Joseph
{"title":"A Distributed Frame Buffer within a Window-Oriented High Performance Graphics System","authors":"T. Haaker, H. Selzer, Hans Joseph","doi":"10.2312/EGGH/EGGH89/261-274","DOIUrl":"https://doi.org/10.2312/EGGH/EGGH89/261-274","url":null,"abstract":"Today's workstation users demand high computational performance combined with powerful graphics and a comfortable window system. Existing and forthcoming standards like OKS-3D, PHIGS/PHIGS+, X Window System, and PEX have to be supported optimally. \u0000 \u0000This paper presents the architecture of a graphics engine designed to meet the above requirements. Utilizing a distributed frame buffer pixel access with a high bandwidth is achieved. Several functions of a window management system like clipping at arbitrarily shaped window boundaries, fast copying of windows and performing Bit-Block-Transfer operations (BitBlT) are performed by hardware. Finally, a homogeneous and load-adaptive multiprocessor configuration for geometry and rendering calculation is described.","PeriodicalId":206166,"journal":{"name":"Advances in Computer Graphics Hardware","volume":"196 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132894754","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A Massively Parallel Approach for the Design of a Raytracing Oriented Architecture 面向光线追踪架构设计的大规模并行方法
Advances in Computer Graphics Hardware Pub Date : 1900-01-01 DOI: 10.2312/EGGH/EGGH88/041-051
T. Muntean, Philippe Waille
{"title":"A Massively Parallel Approach for the Design of a Raytracing Oriented Architecture","authors":"T. Muntean, Philippe Waille","doi":"10.2312/EGGH/EGGH88/041-051","DOIUrl":"https://doi.org/10.2312/EGGH/EGGH88/041-051","url":null,"abstract":"Solving time critical problems requires a computing power of an order of magnitude greater than todays available conventional computers. The use of massively parallel architectures appears to be an attractive and effective way towards the required performances. The ray tracing technique is known as the best synthesis method for the construction of realistic images but also as the most time consuming. Computation time of several hours per image on a conventional mainframe is usual. Fortunately, this technique exhibits a huge amount of potential parallelism and therefore massively parallel architectures fit well and straightforwardly. This paper presents an efficient implementation of the ray tracing algorithm on a dedicated network of transputers. The INMOS's transputers are a family of monochip processors specially designed for parallel, asynchronous architectures without shared memory.","PeriodicalId":206166,"journal":{"name":"Advances in Computer Graphics Hardware","volume":"228 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123875912","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Pixel-Planes 4: A Summary 像素平面4:总结
Advances in Computer Graphics Hardware Pub Date : 1900-01-01 DOI: 10.2312/EGGH/EGGH87/183-207
J. Eyles, J. D. Austin, H. Fuchs, T. Greer, J. Poulton
{"title":"Pixel-Planes 4: A Summary","authors":"J. Eyles, J. D. Austin, H. Fuchs, T. Greer, J. Poulton","doi":"10.2312/EGGH/EGGH87/183-207","DOIUrl":"https://doi.org/10.2312/EGGH/EGGH87/183-207","url":null,"abstract":"We describe the current state of the Pixel-planes research project, whose goal is to develop powerful raster graphics systems for the next generation of workstations, The first full-scale prototype has been in regular use in our department's computer graphics laboratory since its first demonstration at SIGGRAPH '86, more than a year ago, We describe the final hardware configuration of the prototype system, filling in some of the engineering details heretofore unpublished, Next we outline the programming environment for the machine and summarize the major algorithms that have been developed, Finally we discuss our progress towards a new generation of the Pixel-planes architecture, Pixel planes 5.","PeriodicalId":206166,"journal":{"name":"Advances in Computer Graphics Hardware","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121328633","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 31
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