{"title":"PANEL SESSION - Open source hardware IP, are you serious?","authors":"P. Parrish","doi":"10.1109/DATE.2009.5090701","DOIUrl":"https://doi.org/10.1109/DATE.2009.5090701","url":null,"abstract":"You've heard about open source software, but what is open source hardware? Come hear experts from across the industry and in academia discuss the new face of open source, Hardware IP: - What is it? - How are companies and academics using it? - Can Open Source Hardware significantly change the design world?","PeriodicalId":205976,"journal":{"name":"Design, Automation and Test in Europe","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128175580","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Multi-core for mobile phones","authors":"K. V. Berkel","doi":"10.1109/DATE.2009.5090858","DOIUrl":"https://doi.org/10.1109/DATE.2009.5090858","url":null,"abstract":"High-end mobile phones support multiple radio standards and a rich suite of applications, which involves advanced radio, audio, video, and graphics processing. The overall digital workload amounts to nearly 100GOPS, from 4b integer to 24b floating-point operations. With a power budget of only 1W this inevitably leads to heterogeneous multi-core architectures with aggressive power management. We review the state-of-the-art as well as trends.","PeriodicalId":205976,"journal":{"name":"Design, Automation and Test in Europe","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131209229","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
H. Graeb, F. Balasa, R. Castro-López, Yu-Wei Chang, Francisco V. Fernández, Mark Po-Hung Lin, M. Strasser
{"title":"Analog layout synthesis: recent advances in topological approaches","authors":"H. Graeb, F. Balasa, R. Castro-López, Yu-Wei Chang, Francisco V. Fernández, Mark Po-Hung Lin, M. Strasser","doi":"10.1109/DATE.2009.5090670","DOIUrl":"https://doi.org/10.1109/DATE.2009.5090670","url":null,"abstract":"This paper gives an overview of some recent advances in topological approaches to analog layout synthesis and in layout-aware analog sizing. The core issue in these approaches is the modeling of layout constraints for an efficient exploration process. This includes fast checking of constraint compliance, reducing the search space, and quickly relating topological encodings to placements. Sequence-pairs, B*-trees, circuit hierarchy and layout templates are described as advantageous means to tackle these tasks.","PeriodicalId":205976,"journal":{"name":"Design, Automation and Test in Europe","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131447002","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Panel session - ESL methodology for SoC","authors":"L. Toda, W. Rhines","doi":"10.1109/DATE.2009.5090760","DOIUrl":"https://doi.org/10.1109/DATE.2009.5090760","url":null,"abstract":"While electronic system level (ESL) is being adopted in most electronic companies, there is still a need to explore and adopt new methodologies for early design development. Where there have been some successes in the areas of system analysis and virtual prototyping by SoC architects and software developers, investment costs for modelling can be costly or scarce. Also, there is yet to be a standard for applying IP power modelling that fits with a TLM terminology and into the overall system modelling process. Although power is hardly analyzed today even at the RTL level, “access” to power at the ESL domain may become much more critical, given the impact designers can have on power behaviour at this level. Ideally, software developers can also gain visibility into power dynamics and adjust their development flow to accommodate power guidelines, as well. With the current isolated HW and SW flows, this may seem unrealistic. What are some of the pitfalls of being “too early” in applying new technologies? This panel will explore critical issues and possible solutions for designing power applications, enabling engineering teams to rethink their approach to design planning using available ESL tools and methods.","PeriodicalId":205976,"journal":{"name":"Design, Automation and Test in Europe","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122579783","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Panel session - Multicore, will Startups drive innovation?","authors":"A. Jerraya, R. Ernst","doi":"10.1109/DATE.2009.5090883","DOIUrl":"https://doi.org/10.1109/DATE.2009.5090883","url":null,"abstract":"Multicore solution is a need imposed by both technology and market constraints to replace a large part of FPGA and ASIC products for the embedded system market. So far, many solutions featuring a variety of ad-hoc hardware and software multicore architectures have been developed mainly by startups. No clear winning solution has emerged so far to conquer a significant part of this fast growing market. The panel will present the most promising products and solutions and discuss the winning strategy to market.","PeriodicalId":205976,"journal":{"name":"Design, Automation and Test in Europe","volume":"164 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115696591","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Concurrent SoC development and end-to-end planning","authors":"L. Anghel","doi":"10.1109/DATE.2009.5090702","DOIUrl":"https://doi.org/10.1109/DATE.2009.5090702","url":null,"abstract":"SoC development requires interaction between a wide range of engineering disciplines. Each of which brings in optimisation factors that impacts other disciplines. Therefore, concurrent development and end-to-end planning between these disciplines are necessary. This session will show the overlap between design, packaging, silicon manufacturing, test and yield optimisation.","PeriodicalId":205976,"journal":{"name":"Design, Automation and Test in Europe","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132476721","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Strategic directions towards multicore application specific computing","authors":"E. Flamand","doi":"10.1109/DATE.2009.5090859","DOIUrl":"https://doi.org/10.1109/DATE.2009.5090859","url":null,"abstract":"Modern Systems on Chip strongly rely on highly complex, specialized, mixed hardware software sub systems to handle processing intensive tasks: 3D graphic, imaging, video, software radio, positioning... Cost and difficulty of super integration, lack of flexibility, little resource sharing combined with a new class of issues attached to deep submicron process variability, reliability, open opportunities to revisit more regular, programmable approaches as an alternative. Will our industry see the emergence of a new generation of standard mega cells that can be assembled as homogeneous many cores fabrics as an alternative to today's heterogeneous SoCs? We strongly believe that the answer is yes and in this talk we will go through the many folds of this question.","PeriodicalId":205976,"journal":{"name":"Design, Automation and Test in Europe","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126658065","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Consolidation, a modern \"Moor of Venice\" tale","authors":"M. Casale-Rossi, G. Micheli","doi":"10.1109/DATE.2009.5090647","DOIUrl":"https://doi.org/10.1109/DATE.2009.5090647","url":null,"abstract":"\"Othello, The Moor of Venice\" is undoubtedly one of the most famous plays by William Shakespeare, and because of its themes -- love, jealousy and betrayal -- it remains relevant to the present day... and to the electronic industry!","PeriodicalId":205976,"journal":{"name":"Design, Automation and Test in Europe","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115697391","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Trends and challenges in wireless application processors","authors":"Pierre Garnier","doi":"10.1109/DATE.2009.5090738","DOIUrl":"https://doi.org/10.1109/DATE.2009.5090738","url":null,"abstract":"The rapid deployment of 3G wireless networks is accelerating the demand for application processors to deliver multimedia-rich wireless services to end-customers. Texas Instruments has pioneered the way with OMAP(tm) technology. Each generation of OMAP application processors has delivered breakthrough performance with ultra-low power consumption. This challenging combination has been achieved by applying state-of-the art power management technologies to application processors manufactured with leading edge silicon technologies. The trend towards more performance will continue to drive innovation.","PeriodicalId":205976,"journal":{"name":"Design, Automation and Test in Europe","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115638650","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Panel session - Architectures and integration for programmable SoC's","authors":"G. Schreiner, E. Schubert","doi":"10.1109/DATE.2009.5090794","DOIUrl":"https://doi.org/10.1109/DATE.2009.5090794","url":null,"abstract":"With the increasing complexity of designs the requirement for flexibility is also growing. This adds the aspect of programmability to SoC designs. A typical SoC decomposes a system into components which are individually specified. These components are in a pre-existing form that satisfies the specification or are custom-made. With the needed flexibility the decision for components to be hardwired, programmable, or software-based need to be pushed to the end of the design phase. The most desirable situation is that the composition of these components results in the expected system behaviour. The rule, however, is that significant system integration effort is required to make the composition of components operate as intended. To a large extent, this is because of cross-cutting concerns that result from parafunctional characteristics often associated with the integration platform. Ideally, components should be composable (i.e., their properties should not change when connected to other components) and the system should be compositional (i.e., emergent system properties should be derivable from the component properties). Reality is far removed from this situation.","PeriodicalId":205976,"journal":{"name":"Design, Automation and Test in Europe","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122831265","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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