Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07)最新文献_第9页

Litho-aware and low power design of a secure current-based physically unclonable function 基于安全电流的物理不可克隆功能的光刻感知低功耗设计

Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07) Pub Date : 2013-09-04 DOI: 10.1109/ISLPED.2013.6629331

Raghavan Kumar, W. Burleson

引用次数: 8

Holistic approach to low-power system design 低功耗系统设计的整体方法

Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07) Pub Date : 2013-09-04 DOI: 10.1109/ISLPED.2013.6629257

Cheng-Wen Wu

引用次数: 0

Robust and energy-efficient asynchronous dynamic pipelines for ultra-low-voltage operation using adaptive keeper control 采用自适应保持器控制的超低电压异步动态管道鲁棒节能

Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07) Pub Date : 2013-09-04 DOI: 10.1109/ISLPED.2013.6629307

Yu Chen, Mingoo Seok, S. Nowick

{"title":"Robust and energy-efficient asynchronous dynamic pipelines for ultra-low-voltage operation using adaptive keeper control","authors":"Yu Chen, Mingoo Seok, S. Nowick","doi":"10.1109/ISLPED.2013.6629307","DOIUrl":"https://doi.org/10.1109/ISLPED.2013.6629307","url":null,"abstract":"Asynchronous dynamic pipelines are increasingly being used, including in recent commercial design flows, since they simultaneously provide high-performance, clock-free operation and delay-insensitive communication. While they also show promise for energy-efficient ultra-low-voltage circuits, with always-on keepers, these circuits exhibit severe robustness issues. In this paper, an adaptive keeper solution is introduced, to eliminate write contention issues. Arbitrary unknown data rates and congestion must be safely handled, without a reference clock, hence conventional solutions for synchronous design cannot be applied. The proposed method, demonstrated in two widely-used pipelines (PS0, PCHB), directly addresses the asynchronous contention issue by dynamic monitoring of neighboring traffic at each pipeline stage. Simulations of a pipelined ripple-carry adder show correct operation at 0.3 V with energy improvements of up to 4.4× compared to a non-adaptive design. In addition, the approach also improves pipeline throughput by 24.4% and 17.4% at 0.6 V and nominal 1.0 V, respectively.","PeriodicalId":20456,"journal":{"name":"Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07)","volume":"25 1","pages":"267-272"},"PeriodicalIF":0.0,"publicationDate":"2013-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80181890","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Low-power Networks-on-Chip: Progress and remaining challenges 低功耗片上网络:进展与挑战

Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07) Pub Date : 2013-09-04 DOI: 10.1109/ISLPED.2013.6629279

Mark Buckler, W. Burleson, G. Sadowski

引用次数: 12

Understanding query complexity and its implications for energy-efficient web search 了解查询复杂性及其对高能效网络搜索的影响

Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07) Pub Date : 2013-09-04 DOI: 10.1109/ISLPED.2013.6629330

Emily Bragg, Marisabel Guevara, Benjamin C. Lee

引用次数: 5

Automated checkpointing for enabling intensive applications on energy harvesting devices 自动检查点，实现能量收集设备上的密集应用

Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07) Pub Date : 2013-09-04 DOI: 10.1109/ISLPED.2013.6629262

Azalia Mirhoseini, Ebrahim M. Songhori, F. Koushanfar

引用次数: 24

Power mapping and modeling of multi-core processors 多核处理器的功率映射和建模

Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07) Pub Date : 2013-09-04 DOI: 10.5555/2648668.2648680

K. Dev, Abdullah Nazma Nowroz, S. Reda

引用次数: 33

REEL: Reducing effective execution latency of floating point operations REEL:减少浮点操作的有效执行延迟

Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07) Pub Date : 2013-09-04 DOI: 10.1109/ISLPED.2013.6629292

Vignyan Reddy Kothinti Naresh, S. Gilani, Erika Gunadi, N. Kim, M. Schulte, Mikko H. Lipasti

{"title":"REEL: Reducing effective execution latency of floating point operations","authors":"Vignyan Reddy Kothinti Naresh, S. Gilani, Erika Gunadi, N. Kim, M. Schulte, Mikko H. Lipasti","doi":"10.1109/ISLPED.2013.6629292","DOIUrl":"https://doi.org/10.1109/ISLPED.2013.6629292","url":null,"abstract":"The height of the dynamic dependence graph of a program, as executed by a processor, determines the minimum bound on the execution time. This height can be decreased by reducing the effective execution latency of operations that form dependence chains in the graph. In this paper, we propose a technique called REEL to reduce overall latency of chains of dependent floating point (FP) operations by increasing the throughput of computation. REEL comprises of a high-throughput floating point unit (HFP) that allows early issue of an FP Add that is dependent on another FP Add or FP Multiply. This is complemented by instruction scheduler modifications that allow early issue of dependent FP Adds, and a novel checker logic that corrects any precision errors. Unlike conventional static operation fusion, like fused Multiply-Add (FMA), there are no changes to the instruction set to enable utilization of the new hardware, and no recompilation is necessary. Furthermore, unlike ISA-level FMA, our technique produces results that are bit compatible while boosting performance of Add-Add dependence pairs in addition to Multiply-Add pairs. Our evaluation of REEL using CFP2006 benchmarks shows an average performance gain of 7.6% and maximum performance gain of 17% while consuming 1.2% lower energy.","PeriodicalId":20456,"journal":{"name":"Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07)","volume":"75 1","pages":"187-192"},"PeriodicalIF":0.0,"publicationDate":"2013-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72718154","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

An analytical solution for multi-core energy calculation with consideration of leakage and temperature dependency 考虑泄漏和温度依赖的多核能量计算的解析解

Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07) Pub Date : 2013-09-04 DOI: 10.1109/ISLPED.2013.6629322

Ming Fan, Vivek Chaturvedi, Shi Sha, Gang Quan

引用次数: 8

Design and analysis of ultra low power processors using sub/near-threshold 3D stacked ICs 基于亚/近阈值3D堆叠ic的超低功耗处理器设计与分析

Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07) Pub Date : 2013-09-04 DOI: 10.1109/ISLPED.2013.6629261

S. Samal, Yarui Peng, Yang Zhang, S. Lim

引用次数: 2