Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07)最新文献_第9页

Litho-aware and low power design of a secure current-based physically unclonable function 基于安全电流的物理不可克隆功能的光刻感知低功耗设计

Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07) Pub Date : 2013-09-04 DOI: 10.1109/ISLPED.2013.6629331

Raghavan Kumar, W. Burleson

引用次数: 8

Holistic approach to low-power system design 低功耗系统设计的整体方法

Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07) Pub Date : 2013-09-04 DOI: 10.1109/ISLPED.2013.6629257

Cheng-Wen Wu

引用次数: 0

Robust and energy-efficient asynchronous dynamic pipelines for ultra-low-voltage operation using adaptive keeper control 采用自适应保持器控制的超低电压异步动态管道鲁棒节能

Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07) Pub Date : 2013-09-04 DOI: 10.1109/ISLPED.2013.6629307

Yu Chen, Mingoo Seok, S. Nowick

{"title":"Robust and energy-efficient asynchronous dynamic pipelines for ultra-low-voltage operation using adaptive keeper control","authors":"Yu Chen, Mingoo Seok, S. Nowick","doi":"10.1109/ISLPED.2013.6629307","DOIUrl":"https://doi.org/10.1109/ISLPED.2013.6629307","url":null,"abstract":"Asynchronous dynamic pipelines are increasingly being used, including in recent commercial design flows, since they simultaneously provide high-performance, clock-free operation and delay-insensitive communication. While they also show promise for energy-efficient ultra-low-voltage circuits, with always-on keepers, these circuits exhibit severe robustness issues. In this paper, an adaptive keeper solution is introduced, to eliminate write contention issues. Arbitrary unknown data rates and congestion must be safely handled, without a reference clock, hence conventional solutions for synchronous design cannot be applied. The proposed method, demonstrated in two widely-used pipelines (PS0, PCHB), directly addresses the asynchronous contention issue by dynamic monitoring of neighboring traffic at each pipeline stage. Simulations of a pipelined ripple-carry adder show correct operation at 0.3 V with energy improvements of up to 4.4× compared to a non-adaptive design. In addition, the approach also improves pipeline throughput by 24.4% and 17.4% at 0.6 V and nominal 1.0 V, respectively.","PeriodicalId":20456,"journal":{"name":"Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80181890","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Low-power Networks-on-Chip: Progress and remaining challenges 低功耗片上网络:进展与挑战

Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07) Pub Date : 2013-09-04 DOI: 10.1109/ISLPED.2013.6629279

Mark Buckler, W. Burleson, G. Sadowski

引用次数: 12

Understanding query complexity and its implications for energy-efficient web search 了解查询复杂性及其对高能效网络搜索的影响

Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07) Pub Date : 2013-09-04 DOI: 10.1109/ISLPED.2013.6629330

Emily Bragg, Marisabel Guevara, Benjamin C. Lee

引用次数: 5

Automated checkpointing for enabling intensive applications on energy harvesting devices 自动检查点，实现能量收集设备上的密集应用

Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07) Pub Date : 2013-09-04 DOI: 10.1109/ISLPED.2013.6629262

Azalia Mirhoseini, Ebrahim M. Songhori, F. Koushanfar

引用次数: 24

ESPN: A case for energy-star photonic on-chip network ESPN:能源之星光子片上网络的案例

Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07) Pub Date : 2013-09-04 DOI: 10.1109/ISLPED.2013.6629326

Zhongqi Li, Tao Li

引用次数: 7

Variable-energy write STT-RAM architecture with bit-wise write-completion monitoring 可变能量写入STT-RAM架构，具有按位写入完成监控

Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07) Pub Date : 2013-09-04 DOI: 10.1109/ISLPED.2013.6629299

Tianhao Zheng, Jaeyoung Park, M. Orshansky, M. Erez

{"title":"Variable-energy write STT-RAM architecture with bit-wise write-completion monitoring","authors":"Tianhao Zheng, Jaeyoung Park, M. Orshansky, M. Erez","doi":"10.1109/ISLPED.2013.6629299","DOIUrl":"https://doi.org/10.1109/ISLPED.2013.6629299","url":null,"abstract":"In this paper we demonstrate an energy-reduction strategy that relies on the stochastic long-tail nature of the STT-RAM write operation. To move away from the traditional worst-case approach, the per-cell write process is continuously monitored and is terminated as soon as each cell's state matches the written state. Since the average write duration is far shorter than the worst-case duration, the average write energy is significantly reduced by the proposed architecture. We developed a light-weight circuit for fast state change detection and bit-line shutdown and evaluated it using a compact STT-RAM model targeting an implementation in a 16nm technology node. Our analysis indicates that at the required write-error rate the proposed architecture reduces write energy by 87.3%∓99.5% depending on the write direction, and on average achieves 96.5% write energy saving in 16 SPEC CPU 2006 applications compared to conventional design. Compared to the best previously known architecture that exploits stochasticity (verify-on-write), we reduce write energy by approximately 6.5×.","PeriodicalId":20456,"journal":{"name":"Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87013343","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 52

Design and analysis of ultra low power processors using sub/near-threshold 3D stacked ICs 基于亚/近阈值3D堆叠ic的超低功耗处理器设计与分析

Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07) Pub Date : 2013-09-04 DOI: 10.1109/ISLPED.2013.6629261

S. Samal, Yarui Peng, Yang Zhang, S. Lim

引用次数: 2

SIMES: A simulator for hybrid electrical energy storage systems SIMES:混合电能存储系统的模拟器

Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07) Pub Date : 2013-09-04 DOI: 10.1109/ISLPED.2013.6629263

Siyu Yue, Di Zhu, Yanzhi Wang, Massoud Pedram, Younghyun Kim, N. Chang

{"title":"SIMES: A simulator for hybrid electrical energy storage systems","authors":"Siyu Yue, Di Zhu, Yanzhi Wang, Massoud Pedram, Younghyun Kim, N. Chang","doi":"10.1109/ISLPED.2013.6629263","DOIUrl":"https://doi.org/10.1109/ISLPED.2013.6629263","url":null,"abstract":"State-of-the-art electrical energy storage (EES) systems are mainly homogeneous, i.e., they consist of a single type of EES elements. None of the existing EES elements is capable of simultaneously fulfilling all the desired features of an ideal EES system, e.g., high charge/discharge efficiency, high energy density, low cost per unit capacity, long cycle life. A novel technology, i.e., a hybrid EES system that employs heterogeneous EES elements organized in a hierarchy of storage banks and linked by appropriate charge transfer interconnects, has shown great promise in overcoming the aforesaid limitations of conventional EES systems. However, the widespread adoption/deployment of hybrid EES systems is hampered by lack of a hybrid EES system simulator. This paper thus presents SIMES, a powerful and scalable simulator for hybrid EES systems, which provides fast and accurate system simulations, while accounting for key characteristics of various EES elements, power converters, charge transfer interconnect schemes, etc. Experimental results on two different applications (one targeting load shifting for households, the other related to battery rate capacity effect minimization in portable electronic devices) demonstrate the value and usefulness of SIMES for designing energy-aware facilities and products.","PeriodicalId":20456,"journal":{"name":"Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82640013","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 13