Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07)最新文献_第10页

An energy efficient GPGPU memory hierarchy with tiny incoherent caches 具有微小非相干缓存的高能效GPGPU内存层次结构

Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07) Pub Date : 2013-09-04 DOI: 10.1109/ISLPED.2013.6629259

Alamelu Sankaranarayanan, E. K. Ardestani, J. L. Briz, Jose Renau

{"title":"An energy efficient GPGPU memory hierarchy with tiny incoherent caches","authors":"Alamelu Sankaranarayanan, E. K. Ardestani, J. L. Briz, Jose Renau","doi":"10.1109/ISLPED.2013.6629259","DOIUrl":"https://doi.org/10.1109/ISLPED.2013.6629259","url":null,"abstract":"With progressive generations and the ever-increasing promise of computing power, GPGPUs have been quickly growing in size, and at the same time, energy consumption has become a major bottleneck for them. The first level data cache and the scratchpad memory are critical to the performance of a GPGPU, but they are extremely energy inefficient due to the large number of cores they need to serve. This problem could be mitigated by introducing a cache higher up in hierarchy that services fewer cores, but this introduces cache coherency issues that may become very significant, especially for a GPGPU with hundreds of thousands of in-flight threads. In this paper, we propose adding incoherent tinyCaches between each lane in an SM, and the first level data cache that is currently shared by all the lanes in an SM. In a normal multiprocessor, this would require hardware cache coherence between all the SM lanes capable of handling hundreds of thousands of threads. Our incoherent tinyCache architecture exploits certain unique features of the CUDA/OpenCL programming model to avoid complex coherence schemes. This tinyCache is able to filter out 62% of memory requests that would otherwise need to be serviced by the DL1G, and almost 81% of scratchpad memory requests, allowing us to achieve a 37% energy reduction in the on-chip memory hierarchy. We evaluate the tinyCache for different memory patterns and show that it is beneficial in most cases.","PeriodicalId":20456,"journal":{"name":"Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07)","volume":"68 1","pages":"9-14"},"PeriodicalIF":0.0,"publicationDate":"2013-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79553275","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11

Power mapping and modeling of multi-core processors 多核处理器的功率映射和建模

Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07) Pub Date : 2013-09-04 DOI: 10.5555/2648668.2648680

K. Dev, Abdullah Nazma Nowroz, S. Reda

引用次数: 33

An analytical solution for multi-core energy calculation with consideration of leakage and temperature dependency 考虑泄漏和温度依赖的多核能量计算的解析解

Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07) Pub Date : 2013-09-04 DOI: 10.1109/ISLPED.2013.6629322

Ming Fan, Vivek Chaturvedi, Shi Sha, Gang Quan

引用次数: 8

REEL: Reducing effective execution latency of floating point operations REEL:减少浮点操作的有效执行延迟

Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07) Pub Date : 2013-09-04 DOI: 10.1109/ISLPED.2013.6629292

Vignyan Reddy Kothinti Naresh, S. Gilani, Erika Gunadi, N. Kim, M. Schulte, Mikko H. Lipasti

{"title":"REEL: Reducing effective execution latency of floating point operations","authors":"Vignyan Reddy Kothinti Naresh, S. Gilani, Erika Gunadi, N. Kim, M. Schulte, Mikko H. Lipasti","doi":"10.1109/ISLPED.2013.6629292","DOIUrl":"https://doi.org/10.1109/ISLPED.2013.6629292","url":null,"abstract":"The height of the dynamic dependence graph of a program, as executed by a processor, determines the minimum bound on the execution time. This height can be decreased by reducing the effective execution latency of operations that form dependence chains in the graph. In this paper, we propose a technique called REEL to reduce overall latency of chains of dependent floating point (FP) operations by increasing the throughput of computation. REEL comprises of a high-throughput floating point unit (HFP) that allows early issue of an FP Add that is dependent on another FP Add or FP Multiply. This is complemented by instruction scheduler modifications that allow early issue of dependent FP Adds, and a novel checker logic that corrects any precision errors. Unlike conventional static operation fusion, like fused Multiply-Add (FMA), there are no changes to the instruction set to enable utilization of the new hardware, and no recompilation is necessary. Furthermore, unlike ISA-level FMA, our technique produces results that are bit compatible while boosting performance of Add-Add dependence pairs in addition to Multiply-Add pairs. Our evaluation of REEL using CFP2006 benchmarks shows an average performance gain of 7.6% and maximum performance gain of 17% while consuming 1.2% lower energy.","PeriodicalId":20456,"journal":{"name":"Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07)","volume":"75 1","pages":"187-192"},"PeriodicalIF":0.0,"publicationDate":"2013-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72718154","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Coordinated refresh: Energy efficient techniques for DRAM refresh scheduling 协调刷新:DRAM刷新调度的节能技术

Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07) Pub Date : 2013-09-04 DOI: 10.1109/islped.2013.6629295

Ishwar Bhati, Zeshan A. Chishti, B. Jacob

引用次数: 26

Write intensity prediction for energy-efficient non-volatile caches 高能效非易失性缓存的写入强度预测

Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07) Pub Date : 2013-09-04 DOI: 10.1109/ISLPED.2013.6629298

Junwhan Ahn, S. Yoo, Kiyoung Choi

引用次数: 33

Single-cycle, pulse-shaped critical path monitor in the POWER7+ microprocessor POWER7+微处理器中的单周期脉冲形关键路径监视器

Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07) Pub Date : 2013-09-04 DOI: 10.1109/ISLPED.2013.6629293

A. Drake, M. Floyd, Richard L. Willaman, Derek J. Hathaway, J. Hernández, Crystal Soja, Marshall D. Tiner, G. Carpenter, R. Senger

引用次数: 21

Rethinking DC-DC converter design constraints for adaptable systems that target the minimum-energy point 以最小能量点为目标的自适应系统DC-DC变换器设计约束的再思考

Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07) Pub Date : 2013-09-04 DOI: 10.1109/ISLPED.2013.6629327

M. Turnquist, Jani Mäkipää, M. Hiienkari, Hanh-Phuc Le, L. Koskinen

引用次数: 6

Robustness-driven energy-efficient ultra-low voltage standard cell design with intra-cell mixed-Vt methodology 基于胞内混合vt方法的鲁棒驱动节能超低电压标准胞设计

Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07) Pub Date : 2013-09-04 DOI: 10.1109/ISLPED.2013.6629317

Wenfeng Zhao, Yajun Ha, Chin Hau Hoo, A. Alvarez

{"title":"Robustness-driven energy-efficient ultra-low voltage standard cell design with intra-cell mixed-Vt methodology","authors":"Wenfeng Zhao, Yajun Ha, Chin Hau Hoo, A. Alvarez","doi":"10.1109/ISLPED.2013.6629317","DOIUrl":"https://doi.org/10.1109/ISLPED.2013.6629317","url":null,"abstract":"High functional yield is one of the key challenges for subthreshold standard cell designs. Device upsizing is a commonly used but suboptimal method due to its overheads in energy and area. In this paper, we propose a robustness-driven intra-cell mixed-Vt design methodology (MVT-ULV) for the robust ultra-low voltage operation. It uses low threshold voltage transistors in the weak pulling network of logic gates to enhance the robustness. It guarantees the high functional yield with the minimum energy/area overheads. We demonstrate on a commercial 65nm CMOS process that, our proposed design methodology shows up to 60mV and 110mV robustness improvement at 300mV power supply voltage over the commercial library cells and the cells built with previous Leakage-Minimization mixed-Vt methods (MVT-LM) under the same cell area constraints, respectively. In addition, the proposed MVT-ULV library enables ITC'99 benchmark circuits to show on average 30.1% and 78.1% energy-efficiency improvement when compared to the libraries built with the device-upsizing methods and the previous MVT-LM methods under the same yield constraints, respectively.","PeriodicalId":20456,"journal":{"name":"Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07)","volume":"14 1","pages":"323-328"},"PeriodicalIF":0.0,"publicationDate":"2013-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81655411","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

A hybrid display frame buffer architecture for energy efficient display subsystems 一种用于节能显示子系统的混合显示帧缓冲结构

Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07) Pub Date : 2013-09-04 DOI: 10.1109/ISLPED.2013.6629321

Kyungtae Han, Alexander W. Min, Nithyananda S. Jeganathan, Paul Diefenbaugh

{"title":"A hybrid display frame buffer architecture for energy efficient display subsystems","authors":"Kyungtae Han, Alexander W. Min, Nithyananda S. Jeganathan, Paul Diefenbaugh","doi":"10.1109/ISLPED.2013.6629321","DOIUrl":"https://doi.org/10.1109/ISLPED.2013.6629321","url":null,"abstract":"Our principal motivation is to reduce the energy consumption of display subsystems in mobile devices by introducing a hybrid frame buffer architecture into the platform. We observed that display contents on a screen are quite static for certain mobile workloads, such as web browsing. As a result, data reading from the display frame is much more frequent than the writing of new data onto the frame buffer, a state we refer to as read dominance. Based on this observation, we propose a hybrid frame buffer architecture that exploits the display contents' read-dominant property to improve the energy efficiency of display subsystems. Specifically, we employ two memory types: DRAM and Phase-Change Memory (PCM), in the display frame buffer to exploit their different read/write energy characteristics. We also present an analysis of the energy efficiency of the hybrid frame buffer based on our display content and energy consumption models. Our evaluation results show that the proposed hybrid frame buffer reduces frame buffer energy consumption by up to 43%, compared to the conventional DRAM-only frame buffer.","PeriodicalId":20456,"journal":{"name":"Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07)","volume":"79 1","pages":"347-353"},"PeriodicalIF":0.0,"publicationDate":"2013-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85377475","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11