Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07)最新文献_第10页

SIMES: A simulator for hybrid electrical energy storage systems SIMES:混合电能存储系统的模拟器

Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07) Pub Date : 2013-09-04 DOI: 10.1109/ISLPED.2013.6629263

Siyu Yue, Di Zhu, Yanzhi Wang, Massoud Pedram, Younghyun Kim, N. Chang

{"title":"SIMES: A simulator for hybrid electrical energy storage systems","authors":"Siyu Yue, Di Zhu, Yanzhi Wang, Massoud Pedram, Younghyun Kim, N. Chang","doi":"10.1109/ISLPED.2013.6629263","DOIUrl":"https://doi.org/10.1109/ISLPED.2013.6629263","url":null,"abstract":"State-of-the-art electrical energy storage (EES) systems are mainly homogeneous, i.e., they consist of a single type of EES elements. None of the existing EES elements is capable of simultaneously fulfilling all the desired features of an ideal EES system, e.g., high charge/discharge efficiency, high energy density, low cost per unit capacity, long cycle life. A novel technology, i.e., a hybrid EES system that employs heterogeneous EES elements organized in a hierarchy of storage banks and linked by appropriate charge transfer interconnects, has shown great promise in overcoming the aforesaid limitations of conventional EES systems. However, the widespread adoption/deployment of hybrid EES systems is hampered by lack of a hybrid EES system simulator. This paper thus presents SIMES, a powerful and scalable simulator for hybrid EES systems, which provides fast and accurate system simulations, while accounting for key characteristics of various EES elements, power converters, charge transfer interconnect schemes, etc. Experimental results on two different applications (one targeting load shifting for households, the other related to battery rate capacity effect minimization in portable electronic devices) demonstrate the value and usefulness of SIMES for designing energy-aware facilities and products.","PeriodicalId":20456,"journal":{"name":"Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07)","volume":"17 1","pages":"33-38"},"PeriodicalIF":0.0,"publicationDate":"2013-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82640013","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 13

Variable-energy write STT-RAM architecture with bit-wise write-completion monitoring 可变能量写入STT-RAM架构，具有按位写入完成监控

Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07) Pub Date : 2013-09-04 DOI: 10.1109/ISLPED.2013.6629299

Tianhao Zheng, Jaeyoung Park, M. Orshansky, M. Erez

{"title":"Variable-energy write STT-RAM architecture with bit-wise write-completion monitoring","authors":"Tianhao Zheng, Jaeyoung Park, M. Orshansky, M. Erez","doi":"10.1109/ISLPED.2013.6629299","DOIUrl":"https://doi.org/10.1109/ISLPED.2013.6629299","url":null,"abstract":"In this paper we demonstrate an energy-reduction strategy that relies on the stochastic long-tail nature of the STT-RAM write operation. To move away from the traditional worst-case approach, the per-cell write process is continuously monitored and is terminated as soon as each cell's state matches the written state. Since the average write duration is far shorter than the worst-case duration, the average write energy is significantly reduced by the proposed architecture. We developed a light-weight circuit for fast state change detection and bit-line shutdown and evaluated it using a compact STT-RAM model targeting an implementation in a 16nm technology node. Our analysis indicates that at the required write-error rate the proposed architecture reduces write energy by 87.3%∓99.5% depending on the write direction, and on average achieves 96.5% write energy saving in 16 SPEC CPU 2006 applications compared to conventional design. Compared to the best previously known architecture that exploits stochasticity (verify-on-write), we reduce write energy by approximately 6.5×.","PeriodicalId":20456,"journal":{"name":"Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07)","volume":"5 1","pages":"229-234"},"PeriodicalIF":0.0,"publicationDate":"2013-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87013343","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 52

ESPN: A case for energy-star photonic on-chip network ESPN:能源之星光子片上网络的案例

Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07) Pub Date : 2013-09-04 DOI: 10.1109/ISLPED.2013.6629326

Zhongqi Li, Tao Li

引用次数: 7

Coordinated refresh: Energy efficient techniques for DRAM refresh scheduling 协调刷新:DRAM刷新调度的节能技术

Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07) Pub Date : 2013-09-04 DOI: 10.1109/islped.2013.6629295

Ishwar Bhati, Zeshan A. Chishti, B. Jacob

引用次数: 26

An energy efficient GPGPU memory hierarchy with tiny incoherent caches 具有微小非相干缓存的高能效GPGPU内存层次结构

Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07) Pub Date : 2013-09-04 DOI: 10.1109/ISLPED.2013.6629259

Alamelu Sankaranarayanan, E. K. Ardestani, J. L. Briz, Jose Renau

{"title":"An energy efficient GPGPU memory hierarchy with tiny incoherent caches","authors":"Alamelu Sankaranarayanan, E. K. Ardestani, J. L. Briz, Jose Renau","doi":"10.1109/ISLPED.2013.6629259","DOIUrl":"https://doi.org/10.1109/ISLPED.2013.6629259","url":null,"abstract":"With progressive generations and the ever-increasing promise of computing power, GPGPUs have been quickly growing in size, and at the same time, energy consumption has become a major bottleneck for them. The first level data cache and the scratchpad memory are critical to the performance of a GPGPU, but they are extremely energy inefficient due to the large number of cores they need to serve. This problem could be mitigated by introducing a cache higher up in hierarchy that services fewer cores, but this introduces cache coherency issues that may become very significant, especially for a GPGPU with hundreds of thousands of in-flight threads. In this paper, we propose adding incoherent tinyCaches between each lane in an SM, and the first level data cache that is currently shared by all the lanes in an SM. In a normal multiprocessor, this would require hardware cache coherence between all the SM lanes capable of handling hundreds of thousands of threads. Our incoherent tinyCache architecture exploits certain unique features of the CUDA/OpenCL programming model to avoid complex coherence schemes. This tinyCache is able to filter out 62% of memory requests that would otherwise need to be serviced by the DL1G, and almost 81% of scratchpad memory requests, allowing us to achieve a 37% energy reduction in the on-chip memory hierarchy. We evaluate the tinyCache for different memory patterns and show that it is beneficial in most cases.","PeriodicalId":20456,"journal":{"name":"Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07)","volume":"68 1","pages":"9-14"},"PeriodicalIF":0.0,"publicationDate":"2013-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79553275","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11

Write intensity prediction for energy-efficient non-volatile caches 高能效非易失性缓存的写入强度预测

Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07) Pub Date : 2013-09-04 DOI: 10.1109/ISLPED.2013.6629298

Junwhan Ahn, S. Yoo, Kiyoung Choi

引用次数: 33

Single-cycle, pulse-shaped critical path monitor in the POWER7+ microprocessor POWER7+微处理器中的单周期脉冲形关键路径监视器

Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07) Pub Date : 2013-09-04 DOI: 10.1109/ISLPED.2013.6629293

A. Drake, M. Floyd, Richard L. Willaman, Derek J. Hathaway, J. Hernández, Crystal Soja, Marshall D. Tiner, G. Carpenter, R. Senger

引用次数: 21

Rethinking DC-DC converter design constraints for adaptable systems that target the minimum-energy point 以最小能量点为目标的自适应系统DC-DC变换器设计约束的再思考

Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07) Pub Date : 2013-09-04 DOI: 10.1109/ISLPED.2013.6629327

M. Turnquist, Jani Mäkipää, M. Hiienkari, Hanh-Phuc Le, L. Koskinen

引用次数: 6

Robustness-driven energy-efficient ultra-low voltage standard cell design with intra-cell mixed-Vt methodology 基于胞内混合vt方法的鲁棒驱动节能超低电压标准胞设计

Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07) Pub Date : 2013-09-04 DOI: 10.1109/ISLPED.2013.6629317

Wenfeng Zhao, Yajun Ha, Chin Hau Hoo, A. Alvarez

{"title":"Robustness-driven energy-efficient ultra-low voltage standard cell design with intra-cell mixed-Vt methodology","authors":"Wenfeng Zhao, Yajun Ha, Chin Hau Hoo, A. Alvarez","doi":"10.1109/ISLPED.2013.6629317","DOIUrl":"https://doi.org/10.1109/ISLPED.2013.6629317","url":null,"abstract":"High functional yield is one of the key challenges for subthreshold standard cell designs. Device upsizing is a commonly used but suboptimal method due to its overheads in energy and area. In this paper, we propose a robustness-driven intra-cell mixed-Vt design methodology (MVT-ULV) for the robust ultra-low voltage operation. It uses low threshold voltage transistors in the weak pulling network of logic gates to enhance the robustness. It guarantees the high functional yield with the minimum energy/area overheads. We demonstrate on a commercial 65nm CMOS process that, our proposed design methodology shows up to 60mV and 110mV robustness improvement at 300mV power supply voltage over the commercial library cells and the cells built with previous Leakage-Minimization mixed-Vt methods (MVT-LM) under the same cell area constraints, respectively. In addition, the proposed MVT-ULV library enables ITC'99 benchmark circuits to show on average 30.1% and 78.1% energy-efficiency improvement when compared to the libraries built with the device-upsizing methods and the previous MVT-LM methods under the same yield constraints, respectively.","PeriodicalId":20456,"journal":{"name":"Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07)","volume":"14 1","pages":"323-328"},"PeriodicalIF":0.0,"publicationDate":"2013-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81655411","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

A hybrid display frame buffer architecture for energy efficient display subsystems 一种用于节能显示子系统的混合显示帧缓冲结构

Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07) Pub Date : 2013-09-04 DOI: 10.1109/ISLPED.2013.6629321

Kyungtae Han, Alexander W. Min, Nithyananda S. Jeganathan, Paul Diefenbaugh

{"title":"A hybrid display frame buffer architecture for energy efficient display subsystems","authors":"Kyungtae Han, Alexander W. Min, Nithyananda S. Jeganathan, Paul Diefenbaugh","doi":"10.1109/ISLPED.2013.6629321","DOIUrl":"https://doi.org/10.1109/ISLPED.2013.6629321","url":null,"abstract":"Our principal motivation is to reduce the energy consumption of display subsystems in mobile devices by introducing a hybrid frame buffer architecture into the platform. We observed that display contents on a screen are quite static for certain mobile workloads, such as web browsing. As a result, data reading from the display frame is much more frequent than the writing of new data onto the frame buffer, a state we refer to as read dominance. Based on this observation, we propose a hybrid frame buffer architecture that exploits the display contents' read-dominant property to improve the energy efficiency of display subsystems. Specifically, we employ two memory types: DRAM and Phase-Change Memory (PCM), in the display frame buffer to exploit their different read/write energy characteristics. We also present an analysis of the energy efficiency of the hybrid frame buffer based on our display content and energy consumption models. Our evaluation results show that the proposed hybrid frame buffer reduces frame buffer energy consumption by up to 43%, compared to the conventional DRAM-only frame buffer.","PeriodicalId":20456,"journal":{"name":"Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07)","volume":"79 1","pages":"347-353"},"PeriodicalIF":0.0,"publicationDate":"2013-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85377475","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11