Low-power Networks-on-Chip: Progress and remaining challenges

Mark Buckler, W. Burleson, G. Sadowski
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引用次数: 12

Abstract

After a long period of academic and industrial research, networks-on-chips (NoCs) are starting to be incorporated into commercial multi-processor designs. NoCs have proven themselves to scale better than bus-based designs and they are here to stay. It is still important to note, however, that even well-designed NoCs consume a large portion of a given system's power budget. This brief paper and accompanying presentation discuss what options are available to designers who need to reduce NoC power consumption, their benefits, and their limitations. Techniques discussed here include general NoC system design as well as disruptive interconnect mediums and their associated strategies.
低功耗片上网络:进展与挑战
经过长时间的学术和工业研究,片上网络(noc)开始被纳入商业多处理器设计。noc已经证明了自己比基于总线的设计更具有可扩展性,并且它们将继续存在。然而,值得注意的是,即使是设计良好的noc也会消耗给定系统的很大一部分功率预算。这篇简短的论文和随附的演示文稿讨论了需要降低NoC功耗的设计人员可以使用哪些选项,它们的优点和局限性。这里讨论的技术包括一般NoC系统设计以及破坏性互连介质及其相关策略。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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