基于亚/近阈值3D堆叠ic的超低功耗处理器设计与分析

S. Samal, Yarui Peng, Yang Zhang, S. Lim
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引用次数: 2

摘要

在本文中,我们研究了一个三维集成电路微控制器实现的亚阈值电源的超低功耗应用。我们的研究是基于GDSII布局的亚阈值8052微控制器,功耗3.6μW,运行在20 KHz时钟频率和0.4V逻辑电源。我们的研究证实,亚阈值电路确实提供了几个数量级的功率与性能权衡。此外,与2D相比,我们的3D亚阈值设计将占地面积减少了78%,无线长度减少了33%。我们的研究还表明,由于其极低的功耗,在这种亚阈值3D实现中,热和红外下降问题可以忽略不计。最后,我们展示了多核三维亚阈值电路的低功耗和高存储带宽优势。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Design and analysis of ultra low power processors using sub/near-threshold 3D stacked ICs
In this paper, we study a 3D IC micro-controller implemented with sub-threshold supply for ultra-low power applications. Our study is based on GDSII layouts of a sub-threshold 8052 micro-controller that consumes 3.6μW power running at 20 KHz clock frequency and 0.4V logic supply. Our study confirms that sub-threshold circuits indeed offer a few orders of magnitude power vs performance tradeoff. In addition, our 3D sub-threshold design reduces the footprint area by 78% and wirelength by 33% compared with the 2D counterpart. Our studies also show that thermal and IR drop issues are negligible in this sub-threshold 3D implementation due to its extreme low power operation. Lastly, we demonstrate the low power and high memory bandwidth advantages of many-core 3D sub-threshold circuits.
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