发布求助
文献互助 智能选刊 最新文献

Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07)最新文献

筛选
英文 中文
Design and analysis of 3D IC-based low power stereo matching processors 基于三维集成电路的低功耗立体匹配处理器的设计与分析
Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07) Pub Date : 2013-09-04 DOI: 10.1109/ISLPED.2013.6629260
Seung-Ho Ok, Kyeong-Ryeol Bae, S. Lim, Byungin Moon
{"title":"Design and analysis of 3D IC-based low power stereo matching processors","authors":"Seung-Ho Ok, Kyeong-Ryeol Bae, S. Lim, Byungin Moon","doi":"10.1109/ISLPED.2013.6629260","DOIUrl":"https://doi.org/10.1109/ISLPED.2013.6629260","url":null,"abstract":"This paper presents comprehensive design and analysis results of 3D IC-based low-power stereo matching processors. Our design efforts range from architecture design and verification to RTL-to-GDSII design and sign-off analysis based on GlobalFoundries 130-nm PDK. We conduct comprehensive studies on the area, performance, and power benefits of our 3D IC designs over 2D IC designs. Our 2-tier 3D IC designs attain 43% area, 14% wire length, and 13% power saving over 2D IC designs. We also study a pipeline-based partitioning method shown to be effective at minimizing power consumption and the total number of TSVs while balancing the size of each tier.","PeriodicalId":20456,"journal":{"name":"Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07)","volume":"25 1","pages":"15-20"},"PeriodicalIF":0.0,"publicationDate":"2013-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86981746","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Litho-aware and low power design of a secure current-based physically unclonable function 基于安全电流的物理不可克隆功能的光刻感知低功耗设计
Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07) Pub Date : 2013-09-04 DOI: 10.1109/ISLPED.2013.6629331
Raghavan Kumar, W. Burleson
{"title":"Litho-aware and low power design of a secure current-based physically unclonable function","authors":"Raghavan Kumar, W. Burleson","doi":"10.1109/ISLPED.2013.6629331","DOIUrl":"https://doi.org/10.1109/ISLPED.2013.6629331","url":null,"abstract":"Physically Unclonable Functions (PUFs) are lightweight cryptographic primitives for generating unique signatures from complex manufacturing variations. In this work, we present a current-based PUF designed using a generalized lithographic simulation framework for improving inter-die and inter-wafer uniqueness. The sensitivity of the circuit to manufacturing variations is enhanced by placing the gate structures at pitches closer to forbidden zone, where the sensitivity of Critical Dimension (CD) to the pitch variations is very high. Simulation results show that the litho-aware current based PUF has improved inter- and intra-distance over the conventional current-based PUF. The litho-aware PUF consumes about 0.034 pico joules of energy per response bit, which is substantially better than delay-based PUF implementations.","PeriodicalId":20456,"journal":{"name":"Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07)","volume":"58 1","pages":"402-407"},"PeriodicalIF":0.0,"publicationDate":"2013-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78483410","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Holistic approach to low-power system design 低功耗系统设计的整体方法
Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07) Pub Date : 2013-09-04 DOI: 10.1109/ISLPED.2013.6629257
Cheng-Wen Wu
{"title":"Holistic approach to low-power system design","authors":"Cheng-Wen Wu","doi":"10.1109/ISLPED.2013.6629257","DOIUrl":"https://doi.org/10.1109/ISLPED.2013.6629257","url":null,"abstract":"In the past few years, we have witnessed the energy crisis and the financial tsunami that played an unwanted duo, changing the world in many aspects that affect most of us. While companies are working hard in getting out of the slump, many research organizations are rethinking how their R&D budget should be invested. We consider advanced research activities stressing ultra-low power and energy-efficient circuits and systems a top-priority direction. Among our list of R&D topics are ultra-low voltage circuits and systems, energy-harvesting circuits and systems, 3D integration based on the Through-Silicon-Via (TSV) technology, and normally-off computing technologies. To be successful in integrating the basic technologies developed, a holistic approach should be considered. Therefore, in addition to introduction and discussion of the above research topics at ITRI, I will also discuss a system-level modeling and evaluation platform, emphasizing power/energy efficiency.","PeriodicalId":20456,"journal":{"name":"Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07)","volume":"90 1","pages":"2"},"PeriodicalIF":0.0,"publicationDate":"2013-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72974724","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Robust and energy-efficient asynchronous dynamic pipelines for ultra-low-voltage operation using adaptive keeper control 采用自适应保持器控制的超低电压异步动态管道鲁棒节能
Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07) Pub Date : 2013-09-04 DOI: 10.1109/ISLPED.2013.6629307
Yu Chen, Mingoo Seok, S. Nowick
{"title":"Robust and energy-efficient asynchronous dynamic pipelines for ultra-low-voltage operation using adaptive keeper control","authors":"Yu Chen, Mingoo Seok, S. Nowick","doi":"10.1109/ISLPED.2013.6629307","DOIUrl":"https://doi.org/10.1109/ISLPED.2013.6629307","url":null,"abstract":"Asynchronous dynamic pipelines are increasingly being used, including in recent commercial design flows, since they simultaneously provide high-performance, clock-free operation and delay-insensitive communication. While they also show promise for energy-efficient ultra-low-voltage circuits, with always-on keepers, these circuits exhibit severe robustness issues. In this paper, an adaptive keeper solution is introduced, to eliminate write contention issues. Arbitrary unknown data rates and congestion must be safely handled, without a reference clock, hence conventional solutions for synchronous design cannot be applied. The proposed method, demonstrated in two widely-used pipelines (PS0, PCHB), directly addresses the asynchronous contention issue by dynamic monitoring of neighboring traffic at each pipeline stage. Simulations of a pipelined ripple-carry adder show correct operation at 0.3 V with energy improvements of up to 4.4× compared to a non-adaptive design. In addition, the approach also improves pipeline throughput by 24.4% and 17.4% at 0.6 V and nominal 1.0 V, respectively.","PeriodicalId":20456,"journal":{"name":"Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07)","volume":"25 1","pages":"267-272"},"PeriodicalIF":0.0,"publicationDate":"2013-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80181890","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Low-power Networks-on-Chip: Progress and remaining challenges 低功耗片上网络:进展与挑战
Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07) Pub Date : 2013-09-04 DOI: 10.1109/ISLPED.2013.6629279
Mark Buckler, W. Burleson, G. Sadowski
{"title":"Low-power Networks-on-Chip: Progress and remaining challenges","authors":"Mark Buckler, W. Burleson, G. Sadowski","doi":"10.1109/ISLPED.2013.6629279","DOIUrl":"https://doi.org/10.1109/ISLPED.2013.6629279","url":null,"abstract":"After a long period of academic and industrial research, networks-on-chips (NoCs) are starting to be incorporated into commercial multi-processor designs. NoCs have proven themselves to scale better than bus-based designs and they are here to stay. It is still important to note, however, that even well-designed NoCs consume a large portion of a given system's power budget. This brief paper and accompanying presentation discuss what options are available to designers who need to reduce NoC power consumption, their benefits, and their limitations. Techniques discussed here include general NoC system design as well as disruptive interconnect mediums and their associated strategies.","PeriodicalId":20456,"journal":{"name":"Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07)","volume":"1 1","pages":"132-134"},"PeriodicalIF":0.0,"publicationDate":"2013-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83617095","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Understanding query complexity and its implications for energy-efficient web search 了解查询复杂性及其对高能效网络搜索的影响
Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07) Pub Date : 2013-09-04 DOI: 10.1109/ISLPED.2013.6629330
Emily Bragg, Marisabel Guevara, Benjamin C. Lee
{"title":"Understanding query complexity and its implications for energy-efficient web search","authors":"Emily Bragg, Marisabel Guevara, Benjamin C. Lee","doi":"10.1109/ISLPED.2013.6629330","DOIUrl":"https://doi.org/10.1109/ISLPED.2013.6629330","url":null,"abstract":"Today's largest datacenters dissipate megawatts of power. Efficiency is rapidly becoming the primary determinant of datacenter capability. To understand microarchitectural factors that affect efficiency, we must study datacenter workloads.","PeriodicalId":20456,"journal":{"name":"Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07)","volume":"12 1","pages":"401"},"PeriodicalIF":0.0,"publicationDate":"2013-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81019173","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Automated checkpointing for enabling intensive applications on energy harvesting devices 自动检查点，实现能量收集设备上的密集应用
Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07) Pub Date : 2013-09-04 DOI: 10.1109/ISLPED.2013.6629262
Azalia Mirhoseini, Ebrahim M. Songhori, F. Koushanfar
{"title":"Automated checkpointing for enabling intensive applications on energy harvesting devices","authors":"Azalia Mirhoseini, Ebrahim M. Songhori, F. Koushanfar","doi":"10.1109/ISLPED.2013.6629262","DOIUrl":"https://doi.org/10.1109/ISLPED.2013.6629262","url":null,"abstract":"We propose a framework that enables intensive computation on ultra-low power devices with discontinuous energy-harvesting supplies. We devise an optimization algorithm that efficiently partitions the applications into smaller computational steps during high-level synthesis. Our system finds low-overhead checkpoints that minimize recomputation cost due to power losses, then inserts the checkpoints at the design's registertransfer level. The checkpointing rate is automatically adapted to the source's realtime behavior. We evaluate our mechanisms on a battery-less RF energy-harvester platform. Extensive experiments targeting applications in medical implant devices demonstrate our approach's ability to successfully execute complex computations for various supply patterns with low time, energy, and area overheads.","PeriodicalId":20456,"journal":{"name":"Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07)","volume":"95 1","pages":"27-32"},"PeriodicalIF":0.0,"publicationDate":"2013-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86985132","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 24
Write intensity prediction for energy-efficient non-volatile caches 高能效非易失性缓存的写入强度预测
Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07) Pub Date : 2013-09-04 DOI: 10.1109/ISLPED.2013.6629298
Junwhan Ahn, S. Yoo, Kiyoung Choi
{"title":"Write intensity prediction for energy-efficient non-volatile caches","authors":"Junwhan Ahn, S. Yoo, Kiyoung Choi","doi":"10.1109/ISLPED.2013.6629298","DOIUrl":"https://doi.org/10.1109/ISLPED.2013.6629298","url":null,"abstract":"This paper presents a novel concept called write intensity prediction for energy-efficient non-volatile caches as well as the architecture that implements the concept. The key idea is to correlate write intensity of cache blocks with addresses of memory access instructions that incur cache misses of those blocks. The predictor keeps track of instructions that tend to load write-intensive blocks and utilizes that information to predict write intensity of blocks. Based on this concept, we propose a block placement strategy driven by write intensity prediction for SRAM/STT-RAM hybrid caches. Experimental results show that the proposed approach reduces write energy consumption by 55% on average compared to the existing hybrid cache architecture.","PeriodicalId":20456,"journal":{"name":"Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07)","volume":"29 1","pages":"223-228"},"PeriodicalIF":0.0,"publicationDate":"2013-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90362550","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 33
Single-cycle, pulse-shaped critical path monitor in the POWER7+ microprocessor POWER7+微处理器中的单周期脉冲形关键路径监视器
Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07) Pub Date : 2013-09-04 DOI: 10.1109/ISLPED.2013.6629293
A. Drake, M. Floyd, Richard L. Willaman, Derek J. Hathaway, J. Hernández, Crystal Soja, Marshall D. Tiner, G. Carpenter, R. Senger
{"title":"Single-cycle, pulse-shaped critical path monitor in the POWER7+ microprocessor","authors":"A. Drake, M. Floyd, Richard L. Willaman, Derek J. Hathaway, J. Hernández, Crystal Soja, Marshall D. Tiner, G. Carpenter, R. Senger","doi":"10.1109/ISLPED.2013.6629293","DOIUrl":"https://doi.org/10.1109/ISLPED.2013.6629293","url":null,"abstract":"A 32nm SOI critical path monitor (CPM) that can provide timing measurements to a Digital PLL for dynamic frequency adjustments in the 8-core POWER7+™ microprocessor is described. The CPM calibrates to within 2% of cycle time from nominal to turbo voltages. Its voltage sensitivity is 10mV/bit. It tracks processor temperature sensitivity to within 1.5% of nominal frequency, and has a sample jitter less than 1.5% of nominal frequency. The ability to detect noise dynamically allows the system to operate the processor closer to its optimal frequency for any given voltage, resulting in lower voltage for power savings or higher frequency for performance improvements.","PeriodicalId":20456,"journal":{"name":"Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07)","volume":"4 1","pages":"193-198"},"PeriodicalIF":0.0,"publicationDate":"2013-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90511609","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
Rethinking DC-DC converter design constraints for adaptable systems that target the minimum-energy point 以最小能量点为目标的自适应系统DC-DC变换器设计约束的再思考
Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07) Pub Date : 2013-09-04 DOI: 10.1109/ISLPED.2013.6629327
M. Turnquist, Jani Mäkipää, M. Hiienkari, Hanh-Phuc Le, L. Koskinen
{"title":"Rethinking DC-DC converter design constraints for adaptable systems that target the minimum-energy point","authors":"M. Turnquist, Jani Mäkipää, M. Hiienkari, Hanh-Phuc Le, L. Koskinen","doi":"10.1109/ISLPED.2013.6629327","DOIUrl":"https://doi.org/10.1109/ISLPED.2013.6629327","url":null,"abstract":"This paper explores a new DC-DC converter design constraint for adaptable systems that target the minimum-energy point (MEP). Traditionally, DC-DC converters have regulated to a fixed output voltage over a wide range of input voltages. For energy-constrained systems that target the MEP, regulating them to a fixed voltage is unnecessary since changes in the output voltage near the MEP have little impact on the energy per cycle. This paper applies a new and traditional design constraint to a 3:1 series-parallel switched-capacitor (SC) DC-DC converter in 28 nm CMOS. The new design constraint allows for decreased design time, less area, and less system-level energy per cycle compared to traditional constraints.","PeriodicalId":20456,"journal":{"name":"Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07)","volume":"489 1","pages":"383-388"},"PeriodicalIF":0.0,"publicationDate":"2013-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86781943","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
首页 上一页 下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：604180095
Book学术官方微信