具有精确推理的全片上二值化卷积神经网络FPGA实现

Li Yang, Zhezhi He, Deliang Fan
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引用次数: 36

摘要

深度卷积神经网络在机器学习算法中起着重要的作用,在计算机视觉任务中得到了广泛的应用。然而,其庞大的模型尺寸和庞大的计算成本已经成为这种强大算法在低功耗和资源有限的嵌入式系统(如FPGA)中部署的主要障碍。最近的研究表明,利用二值化(即+1和-1)卷积核和二值激活函数的二值化神经网络(BNN)可以显著减小模型尺寸和计算复杂度,为高效节能的FPGA实现铺平了新的道路。在这项工作中,我们首先提出了一种新的BNN算法,称为parallel - convolution BNN(即PC-BNN),它将传统BNN中的原始二进制卷积层替换为两个并行二进制卷积层。PC-BNN在只有2.3Mb参数大小的CIFAR-10数据集上达到~86%。然后,我们将我们提出的PC-BNN部署到只有4.9Mb片上RAM的Xilinx PYNQ Z1 FPGA板上。由于网络参数超小,将整个网络参数存储在片上RAM中是可行的,这样可以大大减少从片外存储器加载网络参数的能量和延迟开销。同时,在PC-BNN FPGA实现中提出了一种新的数据流管道架构,进一步提高了吞吐量。实验结果表明,基于PC-BNN的FPGA实现实现了930帧/秒,387.5 FPS/Watt和396x10-4 FPS/LUT,与最近的工作相比,具有最佳的吞吐量和能效。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A Fully Onchip Binarized Convolutional Neural Network FPGA Impelmentation with Accurate Inference
Deep convolutional neural network has taken an important role in machine learning algorithm which has been widely used in computer vision tasks. However, its enormous model size and massive computation cost have became the main obstacle for deployment of such powerful algorithm in low power and resource limited embedded system, such as FPGA. Recent works have shown the binarized neural networks (BNN), utilizing binarized (i.e. +1 and -1) convolution kernel and binary activation function, can significantly reduce the model size and computation complexity, which paves a new road for energy-efficient FPGA implementation. In this work, we first propose a new BNN algorithm, called Parallel-Convolution BNN (i.e. PC-BNN), which replaces the original binary convolution layer in conventional BNN with two parallel binary convolution layers. PC-BNN achieves ~86% on CIFAR-10 dataset with only 2.3Mb parameter size. We then deploy our proposed PC-BNN into the Xilinx PYNQ Z1 FPGA board with only 4.9Mb on-chip RAM. Since the ultra-small network parameter, it is feasible to store the whole network parameter into on-chip RAM, which could greatly reduce the energy and delay overhead to load network parameter from off-chip memory. Meanwhile, a new data streaming pipeline architecture is proposed in PC-BNN FPGA implementation to further improve throughput. The experiment results show that our PC-BNN based FPGA implementation achieves 930 frames per second, 387.5 FPS/Watt and 396x10-4 FPS/LUT, which are among the best throughput and energy efficiency compared to most recent works.
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